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13342:1ddb43f47325 |
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12-Oct-2018 |
Gabe Black <gabeblack@google.com> |
dev: Explicitly specify the endianness for packet accessors.
Generally speaking, the endianness of the data devices provide or accept is dependent on the device and not the ISA the system executes. This change makes the devices in dev pick an endianness rather than using the guest's.
For the ISA bus and the UART, accesses are byte sized and so endianness doesn't matter. The ISA and PCI busses and the devices which use them are defined to be little endian.
Change-Id: Ib0aa70f192e1d6f3b886d9f3ad41ae03bddb583f Reviewed-on: https://gem5-review.googlesource.com/c/13462 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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11793:ef606668d247 |
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09-Nov-2016 |
Brandon Potter <brandon.potter@amd.com> |
style: [patch 1/22] use /r/3648/ to reorganize includes
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10565:23593fdaadcd |
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02-Dec-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
mem: Remove redundant Packet::allocate calls
This patch cleans up the packet memory allocation confusion. The data is always allocated at the requesting side, when a packet is created (or copied), and there is never a need for any device to allocate any space if it is merely responding to a paket. This behaviour is in line with how SystemC and TLM works as well, thus increasing interoperability, and matching established conventions.
The redundant calls to Packet::allocate are removed, and the checks in the function are tightened up to make sure data is only ever allocated once. There are still some oddities in the packet copy constructor where we copy the data pointer if it is static (without ownership), and allocate new space if the data is dynamic (with ownership). The latter is being worked on further in a follow-on patch.
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10415:85274f24c37a |
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27-Sep-2014 |
Curtis Dunham <Curtis.Dunham@arm.com> |
dev: Output invalid access size in IsaFake panic
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9808:13ffc0066b76 |
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11-Jul-2013 |
Steve Reinhardt <stever@gmail.com> |
dev: make BasicPioDevice take size in constructor
Instead of relying on derived classes explicitly assigning to the BasicPioDevice pioSize field, require them to pass a size value in to the constructor.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
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8461:7d0669201f80 |
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10-Jul-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
IO: Handle case where ISA Fake device is being used as a fake memory.
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8232:b28d06a175be |
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15-Apr-2011 |
Nathan Binkert <nate@binkert.org> |
trace: reimplement the DTRACE function so it doesn't use a vector At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help
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5192:582e583f8e7e |
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31-Oct-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
Traceflags: Add SCons function to created a traceflag instead of having one file with them all.
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5012:c0a28154d002 |
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27-Aug-2007 |
Gabe Black <gblack@eecs.umich.edu> |
Merge with head
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4986:b7c82ad6b3ef |
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24-Aug-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
Mem: Make errors in the memory system be responses, not requests. Fixes cache handling of error responses.
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4918:3214e3694fb2 |
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27-Jul-2007 |
Nathan Binkert <nate@binkert.org> |
Merge python and x86 changes with cache branch
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4870:fcc39d001154 |
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30-Jun-2007 |
Steve Reinhardt <stever@eecs.umich.edu> |
Get rid of Packet result field. Error responses are now encoded in cmd field.
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4762:c94e103c83ad |
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24-Jul-2007 |
Nathan Binkert <nate@binkert.org> |
Major changes to how SimObjects are created and initialized. Almost all creation and initialization now happens in python. Parameter objects are generated and initialized by python. The .ini file is now solely for debugging purposes and is not used in construction of the objects in any way.
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3814:33bd4ec9d66a |
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04-Dec-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
More changes to get SPARC fs closer. Now at 1.2M cycles before difference
configs/common/FSConfig.py: seperate the hypervisor memory and the guest0 memory. In reality we're going to need a better way to do this at some point. Perhaps auto generating the hv-desc image based on the specified config. src/arch/sparc/isa/decoder.isa: change reads/writes to the [hs]tick(cmpr) registers to use readmiscregwitheffect src/arch/sparc/miscregfile.cc: For niagra stick and tick are aliased to one value (if we end up doing mps we might not want this). Use instruction count from cpu rather than cycles because that is what legion does we can change it back after were done with legion src/base/bitfield.hh: add a new function mbits() that just masks off bits of interest but doesn't shift src/cpu/base.cc: src/cpu/base.hh: add instruction count to cpu src/cpu/exetrace.cc: src/cpu/m5legion_interface.h: compare instruction count between legion and m5 too src/cpu/simple/atomic.cc: change asserts of packet success to if panics wrapped with NDEBUG defines so we can get some more useful information when we have a bad address src/dev/isa_fake.cc: src/dev/isa_fake.hh: src/python/m5/objects/Device.py: expand isa fake a bit more having data for each size request, the ability to have writes update the data and to warn on accesses src/python/m5/objects/System.py: convert some tabs to spaces src/python/m5/objects/T1000.py: add more fake devices for each l1 bank and each memory controller
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3502:1ba705a3754b |
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07-Nov-2006 |
Kevin Lim <ktlim@umich.edu> |
Remove hack by setting configuration better.
src/dev/isa_fake.cc: src/dev/isa_fake.hh: No need for specialized init() function any more. src/python/m5/objects/Tsunami.py: Override responder when set by user. This avoids having bus.responder floating around and not doing anything when the user has specified their own default responder.
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3499:597f3f6c9775 |
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06-Nov-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
delete pcifake, tsunamifake. Combine BadAddr/IsaFake into one
src/SConscript: remove pcifake and tsunami fake from sconscript src/dev/isa_fake.cc: src/dev/isa_fake.hh: combine badaddr and isa fake into one src/python/m5/objects/Pci.py: remove pcifake src/python/m5/objects/Tsunami.py: make badaddr derive from isafake
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3488:52e909177bfa |
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02-Nov-2006 |
Kevin Lim <ktlim@umich.edu> |
Implement device that will return BadAddress.
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3357:0963b8a38b5e |
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21-Oct-2006 |
Nathan Binkert <binkertn@umich.edu> |
Missing case
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3349:fec4a86fa212 |
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20-Oct-2006 |
Nathan Binkert <binkertn@umich.edu> |
Use PacketPtr everywhere
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3348:11f6ef023158 |
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20-Oct-2006 |
Nathan Binkert <binkertn@umich.edu> |
refactor code for the packet, get rid of packet_impl.hh and call it packet_access.hh and fix the #includes so things compile right.
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2665:a124942bacb8 |
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31-May-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
Updated Authors from bk prs info
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2662:f24ae2d09e27 |
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30-May-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Minor further cleanup & commenting of Packet class.
src/cpu/simple/atomic.cc: Make common ifetch setup based on Request rather than Packet. Packet::reset() no longer a separate function. sendAtomic() returns latency, not absolute tick. src/cpu/simple/atomic.hh: sendAtomic returns latency, not absolute tick. src/cpu/simple/base.cc: src/cpu/simple/base.hh: src/cpu/simple/timing.cc: Make common ifetch setup based on Request rather than Packet. src/dev/alpha_console.cc: src/dev/ide_ctrl.cc: src/dev/io_device.cc: src/dev/isa_fake.cc: src/dev/ns_gige.cc: src/dev/pciconfigall.cc: src/dev/sinic.cc: src/dev/tsunami_cchip.cc: src/dev/tsunami_io.cc: src/dev/tsunami_pchip.cc: src/dev/uart8250.cc: src/mem/physical.cc: Get rid of redundant Packet time field. src/mem/packet.cc: Eliminate reset() method. src/mem/packet.hh: Fold reset() function into reinitFromRequest()... it was only ever called together with that function. Get rid of redundant time field. Cleanup/add comments. src/mem/port.hh: Document in comment that sendAtomic returns latency, not absolute tick.
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2641:6d9d837e2032 |
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26-May-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Significant rework of Packet class interface: - new constructor guarantees initialization of most fields - flags track status of non-guaranteed fields (addr, size, src) - accessor functions (getAddr() etc.) check status on access - Command & Result classes are nested in Packet class scope - Command now built from vector of behavior bits - string version of Command for tracing - reinitFromRequest() and makeTimingResponse() encapsulate common manipulations of existing packets
src/cpu/simple/atomic.cc: src/cpu/simple/base.cc: src/cpu/simple/timing.cc: src/dev/alpha_console.cc: src/dev/ide_ctrl.cc: src/dev/io_device.cc: src/dev/io_device.hh: src/dev/isa_fake.cc: src/dev/ns_gige.cc: src/dev/pciconfigall.cc: src/dev/sinic.cc: src/dev/tsunami_cchip.cc: src/dev/tsunami_io.cc: src/dev/tsunami_pchip.cc: src/dev/uart8250.cc: src/mem/bus.cc: src/mem/bus.hh: src/mem/physical.cc: src/mem/port.cc: src/mem/port.hh: src/mem/request.hh: Update for new Packet interface.
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2632:1bb2f91485ea |
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22-May-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
New directory structure: - simulator source now in 'src' subdirectory - imported files from 'ext' repository - support building in arbitrary places, including outside of the source tree. See comment at top of SConstruct file for more details. Regression tests are temporarily disabled; that syetem needs more extensive revisions.
SConstruct: Update for new directory structure. Modify to support build trees that are not subdirectories of the source tree. See comment at top of file for more details. Regression tests are temporarily disabled. src/arch/SConscript: src/arch/isa_parser.py: src/python/SConscript: Update for new directory structure.
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