12810SN/A/*
213351Snikos.nikoleris@arm.com * Copyright (c) 2012-2013, 2015-2016, 2018 ARM Limited
39347SAndreas.Sandberg@arm.com * All rights reserved.
49347SAndreas.Sandberg@arm.com *
59347SAndreas.Sandberg@arm.com * The license below extends only to copyright in the software and shall
69347SAndreas.Sandberg@arm.com * not be construed as granting a license to any other intellectual
79347SAndreas.Sandberg@arm.com * property including but not limited to intellectual property relating
89347SAndreas.Sandberg@arm.com * to a hardware implementation of the functionality of the software
99347SAndreas.Sandberg@arm.com * licensed hereunder.  You may use the software subject to the license
109347SAndreas.Sandberg@arm.com * terms below provided that you ensure that this notice is replicated
119347SAndreas.Sandberg@arm.com * unmodified and in its entirety in all distributions of the software,
129347SAndreas.Sandberg@arm.com * modified or unmodified, in source code or in binary form.
139347SAndreas.Sandberg@arm.com *
142810SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan
152810SN/A * All rights reserved.
162810SN/A *
172810SN/A * Redistribution and use in source and binary forms, with or without
182810SN/A * modification, are permitted provided that the following conditions are
192810SN/A * met: redistributions of source code must retain the above copyright
202810SN/A * notice, this list of conditions and the following disclaimer;
212810SN/A * redistributions in binary form must reproduce the above copyright
222810SN/A * notice, this list of conditions and the following disclaimer in the
232810SN/A * documentation and/or other materials provided with the distribution;
242810SN/A * neither the name of the copyright holders nor the names of its
252810SN/A * contributors may be used to endorse or promote products derived from
262810SN/A * this software without specific prior written permission.
272810SN/A *
282810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
292810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
302810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
312810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
322810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
332810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
342810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
352810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
362810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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382810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
392810SN/A *
402810SN/A * Authors: Erik Hallnor
419347SAndreas.Sandberg@arm.com *          Andreas Sandberg
422810SN/A */
432810SN/A
442810SN/A/** @file
452810SN/A * Declaration of a structure to manage MSHRs.
462810SN/A */
472810SN/A
4810764Sandreas.hansson@arm.com#ifndef __MEM_CACHE_MSHR_QUEUE_HH__
4910764Sandreas.hansson@arm.com#define __MEM_CACHE_MSHR_QUEUE_HH__
502810SN/A
5112727Snikos.nikoleris@arm.com#include <string>
524626SN/A
5312727Snikos.nikoleris@arm.com#include "base/types.hh"
548229Snate@binkert.org#include "mem/cache/mshr.hh"
5511375Sandreas.hansson@arm.com#include "mem/cache/queue.hh"
5612727Snikos.nikoleris@arm.com#include "mem/packet.hh"
572810SN/A
582810SN/A/**
593374SN/A * A Class for maintaining a list of pending and allocated memory requests.
602810SN/A */
6111375Sandreas.hansson@arm.comclass MSHRQueue : public Queue<MSHR>
624626SN/A{
632810SN/A  private:
642810SN/A
6510622Smitch.hayenga@arm.com    /**
6610622Smitch.hayenga@arm.com     * The number of entries to reserve for future demand accesses.
6710622Smitch.hayenga@arm.com     * Prevent prefetcher from taking all mshr entries
6810622Smitch.hayenga@arm.com     */
6910622Smitch.hayenga@arm.com    const int demandReserve;
7010622Smitch.hayenga@arm.com
712810SN/A  public:
722810SN/A
732810SN/A    /**
744626SN/A     * Create a queue with a given number of entries.
754626SN/A     * @param num_entrys The number of entries in this queue.
764626SN/A     * @param reserve The minimum number of entries needed to satisfy
774626SN/A     * any access.
7810622Smitch.hayenga@arm.com     * @param demand_reserve The minimum number of entries needed to satisfy
7910622Smitch.hayenga@arm.com     * demand accesses.
802810SN/A     */
815314SN/A    MSHRQueue(const std::string &_label, int num_entries, int reserve,
8211375Sandreas.hansson@arm.com              int demand_reserve);
834920SN/A
842810SN/A    /**
853374SN/A     * Allocates a new MSHR for the request and size. This places the request
862810SN/A     * as the first target in the MSHR.
8710764Sandreas.hansson@arm.com     *
8810764Sandreas.hansson@arm.com     * @param blk_addr The address of the block.
8910764Sandreas.hansson@arm.com     * @param blk_size The number of bytes to request.
9010764Sandreas.hansson@arm.com     * @param pkt The original miss.
9110764Sandreas.hansson@arm.com     * @param when_ready When should the MSHR be ready to act upon.
9210764Sandreas.hansson@arm.com     * @param order The logical order of this MSHR
9311197Sandreas.hansson@arm.com     * @param alloc_on_fill Should the cache allocate a block on fill
9410764Sandreas.hansson@arm.com     *
952810SN/A     * @return The a pointer to the MSHR allocated.
962810SN/A     *
974626SN/A     * @pre There are free entries.
982810SN/A     */
9910764Sandreas.hansson@arm.com    MSHR *allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt,
10011197Sandreas.hansson@arm.com                   Tick when_ready, Counter order, bool alloc_on_fill);
1012810SN/A
1022810SN/A    /**
1034626SN/A     * Moves the MSHR to the front of the pending list if it is not
1044626SN/A     * in service.
1054626SN/A     * @param mshr The entry to move.
1062810SN/A     */
1072810SN/A    void moveToFront(MSHR *mshr);
1082810SN/A
1092810SN/A    /**
11013351Snikos.nikoleris@arm.com     * Adds a delay to the provided MSHR and moves MSHRs that will be
11113351Snikos.nikoleris@arm.com     * ready earlier than this entry to the top of the list
11213351Snikos.nikoleris@arm.com     *
11313351Snikos.nikoleris@arm.com     * @param mshr that needs to be delayed
11413351Snikos.nikoleris@arm.com     * @param delay_ticks ticks of the desired delay
11513351Snikos.nikoleris@arm.com     */
11613351Snikos.nikoleris@arm.com    void delay(MSHR *mshr, Tick delay_ticks);
11713351Snikos.nikoleris@arm.com
11813351Snikos.nikoleris@arm.com    /**
1192810SN/A     * Mark the given MSHR as in service. This removes the MSHR from the
12010679Sandreas.hansson@arm.com     * readyList or deallocates the MSHR if it does not expect a response.
12110679Sandreas.hansson@arm.com     *
1222810SN/A     * @param mshr The MSHR to mark in service.
12311284Sandreas.hansson@arm.com     * @param pending_modified_resp Whether we expect a modified response
12411284Sandreas.hansson@arm.com     *                              from another cache
1252810SN/A     */
12611284Sandreas.hansson@arm.com    void markInService(MSHR *mshr, bool pending_modified_resp);
1272810SN/A
1282810SN/A    /**
1294626SN/A     * Mark an in service entry as pending, used to resend a request.
1302810SN/A     * @param mshr The MSHR to resend.
1312810SN/A     */
1324626SN/A    void markPending(MSHR *mshr);
1332810SN/A
1342810SN/A    /**
13510192Smitch.hayenga@arm.com     * Deallocate top target, possibly freeing the MSHR
13610192Smitch.hayenga@arm.com     * @return if MSHR queue is no longer full
13710192Smitch.hayenga@arm.com     */
13810192Smitch.hayenga@arm.com    bool forceDeallocateTarget(MSHR *mshr);
13910192Smitch.hayenga@arm.com
14010192Smitch.hayenga@arm.com    /**
1412810SN/A     * Returns true if the pending list is not empty.
1423374SN/A     * @return True if there are outstanding requests.
1432810SN/A     */
1442810SN/A    bool havePending() const
1452810SN/A    {
1464666SN/A        return !readyList.empty();
1472810SN/A    }
1482810SN/A
1492810SN/A    /**
15010622Smitch.hayenga@arm.com     * Returns true if sufficient mshrs for prefetch.
15110622Smitch.hayenga@arm.com     * @return True if sufficient mshrs for prefetch.
15210622Smitch.hayenga@arm.com     */
15310622Smitch.hayenga@arm.com    bool canPrefetch() const
15410622Smitch.hayenga@arm.com    {
15511377Sandreas.hansson@arm.com        // @todo we may want to revisit the +1, currently added to
15611377Sandreas.hansson@arm.com        // keep regressions unchanged
15711377Sandreas.hansson@arm.com        return (allocated < numEntries - (numReserve + 1 + demandReserve));
15810622Smitch.hayenga@arm.com    }
1592810SN/A};
1602810SN/A
16110764Sandreas.hansson@arm.com#endif //__MEM_CACHE_MSHR_QUEUE_HH__
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