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/gem5/util/
H A Dprotolib.py10107:524afa92d940 Fri Mar 07 15:56:00 EST 2014 Radhika Jagtap <radhika.jagtap@ARM.com> mem: Edit proto Packet and enhance the python script

This patch changes the decode script to output the optional fields of
the proto message Packet, namely id and flags. The flags field is set
by the communication monitor.

The id field is useful for CPU trace experiments, e.g. linking the
fetch side to decode side. It had to be renamed because it clashes
with a built in python function id() for getting the "identity" of an
object.

This patch also takes a few common function definitions out from the
multiple scripts and adds them to a protolib python module.
H A Dregressdiff 6699:b61018e8d169 Wed Oct 28 14:56:00 EDT 2009 Nathan Binkert <nate@binkert.org> regress: add POWER to regressions
diff 4949:302707329b7e Sun Aug 12 12:56:00 EDT 2007 Nathan Binkert <nate@binkert.org> style: If IGNORE_STYLE=True is set on the scons command line, ignore style.
Use this in the regress script to avoid issues with the checker.
/gem5/configs/topologies/
H A DCluster.pydiff 11669:220fa4099b9a Fri Oct 07 23:56:00 EDT 2016 Tushar Krishna <tushar@ece.gatech.edu> config: fix typo in cluster topology.
/gem5/src/arch/arm/insts/
H A Dvfp.ccdiff 9550:e0e2c8f83d08 Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> scons: Fix up numerous warnings about name shadowing

This patch address the most important name shadowing warnings (as
produced when using gcc/clang with -Wshadow). There are many
locations where constructor parameters and function parameters shadow
local variables, but these are left unchanged.
/gem5/src/mem/
H A Daddr_mapper.hhdiff 9542:683991c46ac8 Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> mem: Add predecessor to SenderState base class

This patch adds a predecessor field to the SenderState base class to
make the process of linking them up more uniform, and enable a
traversal of the stack without knowing the specific type of the
subclasses.

There are a number of simplifications done as part of changing the
SenderState, particularly in the RubyTest.
H A Dmem_delay.hhdiff 12823:ba630bc7a36d Thu Jul 19 13:56:00 EDT 2018 Robert Kovacsics <rmk35@cl.cam.ac.uk> mem: Rename Packet::checkFunctional to trySatisfyFunctional

Packet::checkFunctional also wrote data to/from the packet depending
on if it was read/write, respectively, which the 'check' in the name
would suggest otherwise. This renames it to doFunctional, which is
more suggestive. It also renames any function called checkFunctional
which calls Packet::checkFunctional. These are

- Bridge::BridgeMasterPort::checkFunctional
- calls Packet::checkFunctional
- MSHR::checkFunctional
- calls Packet::checkFunctional
- MSHR::TargetList::checkFunctional
- calls Packet::checkFunctional
- Queue<>::checkFunctional
(of src/mem/cache/queue.hh, not src/cpu/minor/buffers.h)
- Instantiated with Queue<WriteQueueEntry> and Queue<MSHR>
- WriteQueueEntry
- calls Packet::checkFunctional
- WriteQueueEntry::TargetList
- calls Packet::checkFunctional
- MemDelay::checkFunctional
- calls QueuedSlavePort/QueuedMasterPort::checkFunctional
- Packet::checkFunctional
- PacketQueue::checkFunctional
- calls Packet::checkFunctional
- QueuedSlavePort::checkFunctional
- calls PacketQueue::doFunctional
- QueuedMasterPort::checkFunctional
- calls PacketQueue::doFunctional
- SerialLink::SerialLinkMasterPort::checkFunctional
- calls Packet::doFunctional

Change-Id: Ieca2579c020c329040da053ba8e25820801b62c5
Reviewed-on: https://gem5-review.googlesource.com/11810
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
H A Dmem_delay.ccdiff 12823:ba630bc7a36d Thu Jul 19 13:56:00 EDT 2018 Robert Kovacsics <rmk35@cl.cam.ac.uk> mem: Rename Packet::checkFunctional to trySatisfyFunctional

Packet::checkFunctional also wrote data to/from the packet depending
on if it was read/write, respectively, which the 'check' in the name
would suggest otherwise. This renames it to doFunctional, which is
more suggestive. It also renames any function called checkFunctional
which calls Packet::checkFunctional. These are

- Bridge::BridgeMasterPort::checkFunctional
- calls Packet::checkFunctional
- MSHR::checkFunctional
- calls Packet::checkFunctional
- MSHR::TargetList::checkFunctional
- calls Packet::checkFunctional
- Queue<>::checkFunctional
(of src/mem/cache/queue.hh, not src/cpu/minor/buffers.h)
- Instantiated with Queue<WriteQueueEntry> and Queue<MSHR>
- WriteQueueEntry
- calls Packet::checkFunctional
- WriteQueueEntry::TargetList
- calls Packet::checkFunctional
- MemDelay::checkFunctional
- calls QueuedSlavePort/QueuedMasterPort::checkFunctional
- Packet::checkFunctional
- PacketQueue::checkFunctional
- calls Packet::checkFunctional
- QueuedSlavePort::checkFunctional
- calls PacketQueue::doFunctional
- QueuedMasterPort::checkFunctional
- calls PacketQueue::doFunctional
- SerialLink::SerialLinkMasterPort::checkFunctional
- calls Packet::doFunctional

Change-Id: Ieca2579c020c329040da053ba8e25820801b62c5
Reviewed-on: https://gem5-review.googlesource.com/11810
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
H A Dserial_link.hhdiff 12823:ba630bc7a36d Thu Jul 19 13:56:00 EDT 2018 Robert Kovacsics <rmk35@cl.cam.ac.uk> mem: Rename Packet::checkFunctional to trySatisfyFunctional

Packet::checkFunctional also wrote data to/from the packet depending
on if it was read/write, respectively, which the 'check' in the name
would suggest otherwise. This renames it to doFunctional, which is
more suggestive. It also renames any function called checkFunctional
which calls Packet::checkFunctional. These are

- Bridge::BridgeMasterPort::checkFunctional
- calls Packet::checkFunctional
- MSHR::checkFunctional
- calls Packet::checkFunctional
- MSHR::TargetList::checkFunctional
- calls Packet::checkFunctional
- Queue<>::checkFunctional
(of src/mem/cache/queue.hh, not src/cpu/minor/buffers.h)
- Instantiated with Queue<WriteQueueEntry> and Queue<MSHR>
- WriteQueueEntry
- calls Packet::checkFunctional
- WriteQueueEntry::TargetList
- calls Packet::checkFunctional
- MemDelay::checkFunctional
- calls QueuedSlavePort/QueuedMasterPort::checkFunctional
- Packet::checkFunctional
- PacketQueue::checkFunctional
- calls Packet::checkFunctional
- QueuedSlavePort::checkFunctional
- calls PacketQueue::doFunctional
- QueuedMasterPort::checkFunctional
- calls PacketQueue::doFunctional
- SerialLink::SerialLinkMasterPort::checkFunctional
- calls Packet::doFunctional

Change-Id: Ieca2579c020c329040da053ba8e25820801b62c5
Reviewed-on: https://gem5-review.googlesource.com/11810
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
H A Dsecure_port_proxy.hh14007:36f842f523c6 Wed May 01 20:56:00 EDT 2019 Gabe Black <gabeblack@google.com> arm, mem: Move the SecurePortProxy subclass into it's own file.

The idea of a "secure" memory area/access is specific to ARM and
shouldn't be in the common mem directory, although it's built in to the
generic memory protocol at this point.

Regardless, it should minimially be in its own file like the virtual
and physical port proxy classes are.

Change-Id: I140d4566ee2deded784adb04bcf6f11755a85c0c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18569
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
/gem5/src/systemc/
H A DSConscriptdiff 13873:9fd9b551f9d8 Mon Apr 15 22:56:00 EDT 2019 Gabe Black <gabeblack@google.com> systemc: Add Port types for initiator and target sockets.

These make it clear that a port represents a TLM socket, what direction
it faces, and what its width is.

Change-Id: Idcbea2b9b053f1e0685e011bc2c7de2468fb25b2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18172
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
/gem5/src/dev/arm/
H A Dsmmu_v3_cmdexec.ccdiff 14064:870553bad072 Tue Jun 18 11:56:00 EDT 2019 Adrian Herrera <adrian.herrera@arm.com> dev-arm: drain implementation for SMMUv3

SMMUv3 is drained when (1) no SMMU translations are pending
on any of its slave interfaces and (2) no commands are stored
in the Command Queue waiting to be processed.

Change-Id: I81cef5fd821fa5e509e130af02aece5239493df5
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19309
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
H A Dsmmu_v3_slaveifc.hhdiff 14064:870553bad072 Tue Jun 18 11:56:00 EDT 2019 Adrian Herrera <adrian.herrera@arm.com> dev-arm: drain implementation for SMMUv3

SMMUv3 is drained when (1) no SMMU translations are pending
on any of its slave interfaces and (2) no commands are stored
in the Command Queue waiting to be processed.

Change-Id: I81cef5fd821fa5e509e130af02aece5239493df5
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19309
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
/gem5/src/dev/x86/
H A DSConscriptdiff 9807:63d7362bbdf2 Thu Jul 11 22:56:00 EDT 2013 Steve Reinhardt <stever@gmail.com> dev: consistently end device classes in 'Device'

PciDev and IntDev stuck out as the only device classes that
ended in 'Dev' rather than 'Device'. This patch takes care
of that inconsistency.

Note that you may need to delete pre-existing files matching
build/*/python/m5/internal/param_* as scons does not pick up
indirect dependencies on imported python modules when generating
params, and the PciDev -> PciDevice rename takes place in a
file (dev/Device.py) that gets imported quite a bit.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
H A Di8259.ccdiff 9807:63d7362bbdf2 Thu Jul 11 22:56:00 EDT 2013 Steve Reinhardt <stever@gmail.com> dev: consistently end device classes in 'Device'

PciDev and IntDev stuck out as the only device classes that
ended in 'Dev' rather than 'Device'. This patch takes care
of that inconsistency.

Note that you may need to delete pre-existing files matching
build/*/python/m5/internal/param_* as scons does not pick up
indirect dependencies on imported python modules when generating
params, and the PciDev -> PciDevice rename takes place in a
file (dev/Device.py) that gets imported quite a bit.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
diff 5830:1758d56964c9 Sun Feb 01 02:56:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Set up the console interrupt and add some DPRINTFs.
/gem5/src/mem/ruby/network/simple/
H A DPerfectSwitch.hhdiff 9554:406fbcf60223 Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> scons: Add warning for missing declarations

This patch enables warnings for missing declarations. To avoid issues
with SWIG-generated code, the warning is only applied to non-SWIG
code.
diff 7054:7d6862b80049 Wed Mar 31 19:56:00 EDT 2010 Nathan Binkert <nate@binkert.org> style: another ruby style pass
/gem5/src/mem/cache/
H A Dmshr.ccdiff 12823:ba630bc7a36d Thu Jul 19 13:56:00 EDT 2018 Robert Kovacsics <rmk35@cl.cam.ac.uk> mem: Rename Packet::checkFunctional to trySatisfyFunctional

Packet::checkFunctional also wrote data to/from the packet depending
on if it was read/write, respectively, which the 'check' in the name
would suggest otherwise. This renames it to doFunctional, which is
more suggestive. It also renames any function called checkFunctional
which calls Packet::checkFunctional. These are

- Bridge::BridgeMasterPort::checkFunctional
- calls Packet::checkFunctional
- MSHR::checkFunctional
- calls Packet::checkFunctional
- MSHR::TargetList::checkFunctional
- calls Packet::checkFunctional
- Queue<>::checkFunctional
(of src/mem/cache/queue.hh, not src/cpu/minor/buffers.h)
- Instantiated with Queue<WriteQueueEntry> and Queue<MSHR>
- WriteQueueEntry
- calls Packet::checkFunctional
- WriteQueueEntry::TargetList
- calls Packet::checkFunctional
- MemDelay::checkFunctional
- calls QueuedSlavePort/QueuedMasterPort::checkFunctional
- Packet::checkFunctional
- PacketQueue::checkFunctional
- calls Packet::checkFunctional
- QueuedSlavePort::checkFunctional
- calls PacketQueue::doFunctional
- QueuedMasterPort::checkFunctional
- calls PacketQueue::doFunctional
- SerialLink::SerialLinkMasterPort::checkFunctional
- calls Packet::doFunctional

Change-Id: Ieca2579c020c329040da053ba8e25820801b62c5
Reviewed-on: https://gem5-review.googlesource.com/11810
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
diff 12727:56c23b54bcb1 Wed May 02 19:14:00 EDT 2018 Nikos Nikoleris <nikos.nikoleris@arm.com> mem-cache: Fix include directives in the cache related classes

Change-Id: I111b0f662897c43974aadb08da1ed85c7542585c
Reviewed-on: https://gem5-review.googlesource.com/10433
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
diff 11490:e03a6233d061 Thu May 26 06:56:00 EDT 2016 Andreas Hansson <andreas.hansson@arm.com> mem: Do not set cacheResponding on MSHR snoop if not responding

This patch changes the flow control for HSHR::handleSnoop to ensure
that we only set cacheResponding on the snoop packet if we are
actually responding. This avoids situations where a responder is
stalling indefinitely on a response that never arrives.

Change-Id: I691dd01755b614b30203581aa74fc743b350eacc
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
diff 11486:f09bb73b3050 Thu May 26 06:56:00 EDT 2016 Nikos Nikoleris <nikos.nikoleris@arm.com> mem: fix headers include order in the cache related classes

Change-Id: Ia57cc104978861ab342720654e408dbbfcbe4b69
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
diff 11484:08b33c52a16d Thu May 26 06:56:00 EDT 2016 Nikos Nikoleris <nikos.nikoleris@arm.com> mem: change NULL to nullptr in the cache related classes

Change-Id: I5042410be54935650b7d05c84d8d9efbfcc06e70
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
diff 10768:9a34e28cd2c2 Fri Mar 27 04:56:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> mem: Ignore uncacheable MSHRs when finding matches

This patch changes how we search for matching MSHRs, ignoring any MSHR
that is allocated for an uncacheable access. By doing so, this patch
fixes a corner case in the MSHRs where incorrect data ended up being
copied into a (cacheable) read packet due to a first uncacheable MSHR
target of size 4, followed by a cacheable target to the same MSHR of
size 64. The latter target was filled with nonsense data.
diff 9543:a373b2e664ff Tue Feb 19 05:56:00 EST 2013 Sascha Bischoff <sascha.bischoff@arm.com> mem: Fix SenderState related cache deadlock

This patch fixes a potential deadlock in the caches. This deadlock
could occur when more than one cache is used in a system, and
pkt->senderState is modified in between the two caches. This happened
as the caches relied on the senderState remaining unchanged, and used
it for instantaneous upstream communication with other caches.

This issue has been addressed by iterating over the linked list of
senderStates until we are either able to cast to a MSHR* or
senderState is NULL. If the cast is successful, we know that the
packet has previously passed through another cache, and therefore
update the downstreamPending flag accordingly. Otherwise, we do
nothing.
diff 5875:d82be3235ab4 Mon Feb 16 11:56:00 EST 2009 Steve Reinhardt <steve.reinhardt@amd.com> Fixes to get prefetching working again.
Apparently we broke it with the cache rewrite and never noticed.
Thanks to Bao Yungang <baoyungang@gmail.com> for a significant part
of these changes (and for inspiring me to work on the rest).
Some other overdue cleanup on the prefetch code too.
H A Dmshr_queue.ccdiff 12727:56c23b54bcb1 Wed May 02 19:14:00 EDT 2018 Nikos Nikoleris <nikos.nikoleris@arm.com> mem-cache: Fix include directives in the cache related classes

Change-Id: I111b0f662897c43974aadb08da1ed85c7542585c
Reviewed-on: https://gem5-review.googlesource.com/10433
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
diff 10768:9a34e28cd2c2 Fri Mar 27 04:56:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> mem: Ignore uncacheable MSHRs when finding matches

This patch changes how we search for matching MSHRs, ignoring any MSHR
that is allocated for an uncacheable access. By doing so, this patch
fixes a corner case in the MSHRs where incorrect data ended up being
copied into a (cacheable) read packet due to a first uncacheable MSHR
target of size 4, followed by a cacheable target to the same MSHR of
size 64. The latter target was filled with nonsense data.
/gem5/src/arch/x86/
H A Dinterrupts.ccdiff 9807:63d7362bbdf2 Thu Jul 11 22:56:00 EDT 2013 Steve Reinhardt <stever@gmail.com> dev: consistently end device classes in 'Device'

PciDev and IntDev stuck out as the only device classes that
ended in 'Dev' rather than 'Device'. This patch takes care
of that inconsistency.

Note that you may need to delete pre-existing files matching
build/*/python/m5/internal/param_* as scons does not pick up
indirect dependencies on imported python modules when generating
params, and the PciDev -> PciDevice rename takes place in a
file (dev/Device.py) that gets imported quite a bit.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
diff 9805:a4339e26b429 Thu Jul 11 22:56:00 EDT 2013 Steve Reinhardt <stever@gmail.com> devices: make more classes derive from BasicPioDevice
A couple of devices that have single fixed memory mapped regions
were not derived from BasicPioDevice, when that's exactly
the functionality that BasicPioDevice provides. This patch
gets rid of a little bit of redundant code by making those
devices actually do so.

Also fixed the weird case of X86ISA::Interrupts, where
the class already did derive from BasicPioDevice but
didn't actually use all the features it could have.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
diff 9557:8666e81607a6 Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> scons: Fix warnings issued by clang 3.2svn (XCode 4.6)

This patch fixes the warnings that clang3.2svn emit due to the "-Wall"
flag. There is one case of an uninitialised value in the ARM neon ISA
description, and then a whole range of unused private fields that are
pruned.
diff 9544:1a075d9bc1bc Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> x86: Move APIC clock divider to Python

This patch moves the 16x APIC clock divider to the Python code to
avoid the post-instantiation modifications to the clock. The x86 APIC
was the only object setting the clock after creation time and this
required some custom functionality and configuration. With this patch,
the clock multiplier is moved to the Python code and the objects are
instantiated with the appropriate clock.
diff 6066:a9fe0813039f Sun Apr 19 06:56:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Only recognize the first startup IPI after INIT or reset.
diff 6065:0ad264b74ac2 Sun Apr 19 06:56:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Use recvResponse to implement the idle bit in the Local APIC ICR.
H A Dinterrupts.hhdiff 9807:63d7362bbdf2 Thu Jul 11 22:56:00 EDT 2013 Steve Reinhardt <stever@gmail.com> dev: consistently end device classes in 'Device'

PciDev and IntDev stuck out as the only device classes that
ended in 'Dev' rather than 'Device'. This patch takes care
of that inconsistency.

Note that you may need to delete pre-existing files matching
build/*/python/m5/internal/param_* as scons does not pick up
indirect dependencies on imported python modules when generating
params, and the PciDev -> PciDevice rename takes place in a
file (dev/Device.py) that gets imported quite a bit.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
diff 9805:a4339e26b429 Thu Jul 11 22:56:00 EDT 2013 Steve Reinhardt <stever@gmail.com> devices: make more classes derive from BasicPioDevice
A couple of devices that have single fixed memory mapped regions
were not derived from BasicPioDevice, when that's exactly
the functionality that BasicPioDevice provides. This patch
gets rid of a little bit of redundant code by making those
devices actually do so.

Also fixed the weird case of X86ISA::Interrupts, where
the class already did derive from BasicPioDevice but
didn't actually use all the features it could have.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
diff 9554:406fbcf60223 Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> scons: Add warning for missing declarations

This patch enables warnings for missing declarations. To avoid issues
with SWIG-generated code, the warning is only applied to non-SWIG
code.
diff 9544:1a075d9bc1bc Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> x86: Move APIC clock divider to Python

This patch moves the 16x APIC clock divider to the Python code to
avoid the post-instantiation modifications to the clock. The x86 APIC
was the only object setting the clock after creation time and this
required some custom functionality and configuration. With this patch,
the clock multiplier is moved to the Python code and the objects are
instantiated with the appropriate clock.
diff 6066:a9fe0813039f Sun Apr 19 06:56:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Only recognize the first startup IPI after INIT or reset.
/gem5/src/mem/cache/prefetch/
H A Dbase.hhdiff 12727:56c23b54bcb1 Wed May 02 19:14:00 EDT 2018 Nikos Nikoleris <nikos.nikoleris@arm.com> mem-cache: Fix include directives in the cache related classes

Change-Id: I111b0f662897c43974aadb08da1ed85c7542585c
Reviewed-on: https://gem5-review.googlesource.com/10433
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
diff 9546:ac0c18d738ce Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> mem: Add deferred packet class to prefetcher

This patch removes the time field from the packet as it was only used
by the preftecher. Similar to the packet queue, the prefetcher now
wraps the packet in a deferred packet, which also has a tick
representing the absolute time when the packet should be sent.
diff 5875:d82be3235ab4 Mon Feb 16 11:56:00 EST 2009 Steve Reinhardt <steve.reinhardt@amd.com> Fixes to get prefetching working again.
Apparently we broke it with the cache rewrite and never noticed.
Thanks to Bao Yungang <baoyungang@gmail.com> for a significant part
of these changes (and for inspiring me to work on the rest).
Some other overdue cleanup on the prefetch code too.
H A Dqueued.ccdiff 12727:56c23b54bcb1 Wed May 02 19:14:00 EDT 2018 Nikos Nikoleris <nikos.nikoleris@arm.com> mem-cache: Fix include directives in the cache related classes

Change-Id: I111b0f662897c43974aadb08da1ed85c7542585c
Reviewed-on: https://gem5-review.googlesource.com/10433
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
diff 11484:08b33c52a16d Thu May 26 06:56:00 EDT 2016 Nikos Nikoleris <nikos.nikoleris@arm.com> mem: change NULL to nullptr in the cache related classes

Change-Id: I5042410be54935650b7d05c84d8d9efbfcc06e70
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
/gem5/src/cpu/minor/
H A Dexecute.ccdiff 13966:3189413c5894 Fri Mar 01 08:56:00 EST 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> Revert "cpu: fix how a thread starts up in MinorCPU"

This reverts commit 02dafc5498750d9734ba8f2a1608a846f90b71d1.
The commit was part of a patchset which broke MinorCPU regressions
(switcheroo)

Change-Id: I0a8098fc71abe5838014e587dbe372b258d8aa9f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18604
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
diff 13965:347e04956cfe Fri Mar 01 08:56:00 EST 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> Revert "cpu: stop scheduling suspended threads in MinorCPU"

This reverts commit 6a6668bbc4b038b98eb3ee64ffb034719316afd9.
The commit was part of a patchset which broke MinorCPU regressions
(switcheroo)

Change-Id: I3c16a6478ba44b9d27cdd3d64a710a356999df05
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18603
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
diff 13964:e4dbd156a640 Fri Mar 01 08:56:00 EST 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> Revert "cpu: fix branching when thread is suspended in MinorCPU"

This reverts commit e437086341712f1435db655b3527ea29b3311f4e.
The commit was part of a patchset which broke MinorCPU regressions
(switcheroo)

Change-Id: Ib8482034c2402008ccfa552325a8eb31e731b619
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18602
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
H A Dfetch2.ccdiff 13966:3189413c5894 Fri Mar 01 08:56:00 EST 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> Revert "cpu: fix how a thread starts up in MinorCPU"

This reverts commit 02dafc5498750d9734ba8f2a1608a846f90b71d1.
The commit was part of a patchset which broke MinorCPU regressions
(switcheroo)

Change-Id: I0a8098fc71abe5838014e587dbe372b258d8aa9f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18604
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
diff 13965:347e04956cfe Fri Mar 01 08:56:00 EST 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> Revert "cpu: stop scheduling suspended threads in MinorCPU"

This reverts commit 6a6668bbc4b038b98eb3ee64ffb034719316afd9.
The commit was part of a patchset which broke MinorCPU regressions
(switcheroo)

Change-Id: I3c16a6478ba44b9d27cdd3d64a710a356999df05
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18603
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
/gem5/src/sim/
H A Dstat_control.ccdiff 9450:35d4879ad7c2 Mon Jan 07 16:56:00 EST 2013 Sascha Bischoff <sascha.bischoff@arm.com> stats: Fix swig wrapping for Tick in stats

Tick was not correctly wrapped for the stats system, and therefore it was not
possible to configure the stats dumping from the python scripts without
defining Ticks as long long. This patch fixes the wrapping of Tick by copying
the typemap of uint64_t to Tick.
diff 8581:56f97760eadd Thu Sep 22 21:59:00 EDT 2011 Steve Reinhardt <steve.reinhardt@amd.com> event: minor cleanup
Initialize flags via the Event constructor instead of calling
setFlags() in the body of the derived class's constructor. I
forget exactly why, but this made life easier when implementing
multi-queue support.

Also rename Event::getFlags() to isFlagSet() to better match
common usage, and get rid of some unused Event methods.
/gem5/src/mem/ruby/network/
H A DNetwork.ccdiff 7054:7d6862b80049 Wed Mar 31 19:56:00 EDT 2010 Nathan Binkert <nate@binkert.org> style: another ruby style pass
diff 6700:deb871e1fc27 Wed Oct 28 14:56:00 EDT 2009 Nathan Binkert <nate@binkert.org> license: Fix license on network model code

This mostly was a matter of changing the license owner to Princeton
which is as it should have been. The code was originally licensed
under the GPL but was relicensed as BSD by Li-Shiuan Peh on July 27,
2009. This relicensing was in an explicit e-mail to Nathan Binkert,
Brad Beckmann, Mark Hill, David Wood, and Steve Reinhardt.

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