114039Sstacze01@arm.com/* 214039Sstacze01@arm.com * Copyright (c) 2013, 2018-2019 ARM Limited 314039Sstacze01@arm.com * All rights reserved 414039Sstacze01@arm.com * 514039Sstacze01@arm.com * The license below extends only to copyright in the software and shall 614039Sstacze01@arm.com * not be construed as granting a license to any other intellectual 714039Sstacze01@arm.com * property including but not limited to intellectual property relating 814039Sstacze01@arm.com * to a hardware implementation of the functionality of the software 914039Sstacze01@arm.com * licensed hereunder. You may use the software subject to the license 1014039Sstacze01@arm.com * terms below provided that you ensure that this notice is replicated 1114039Sstacze01@arm.com * unmodified and in its entirety in all distributions of the software, 1214039Sstacze01@arm.com * modified or unmodified, in source code or in binary form. 1314039Sstacze01@arm.com * 1414039Sstacze01@arm.com * Redistribution and use in source and binary forms, with or without 1514039Sstacze01@arm.com * modification, are permitted provided that the following conditions are 1614039Sstacze01@arm.com * met: redistributions of source code must retain the above copyright 1714039Sstacze01@arm.com * notice, this list of conditions and the following disclaimer; 1814039Sstacze01@arm.com * redistributions in binary form must reproduce the above copyright 1914039Sstacze01@arm.com * notice, this list of conditions and the following disclaimer in the 2014039Sstacze01@arm.com * documentation and/or other materials provided with the distribution; 2114039Sstacze01@arm.com * neither the name of the copyright holders nor the names of its 2214039Sstacze01@arm.com * contributors may be used to endorse or promote products derived from 2314039Sstacze01@arm.com * this software without specific prior written permission. 2414039Sstacze01@arm.com * 2514039Sstacze01@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2614039Sstacze01@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2714039Sstacze01@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2814039Sstacze01@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2914039Sstacze01@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3014039Sstacze01@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3114039Sstacze01@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3214039Sstacze01@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3314039Sstacze01@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3414039Sstacze01@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3514039Sstacze01@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3614039Sstacze01@arm.com * 3714039Sstacze01@arm.com * Authors: Stan Czerniawski 3814039Sstacze01@arm.com */ 3914039Sstacze01@arm.com 4014039Sstacze01@arm.com#ifndef __DEV_ARM_SMMU_V3_SLAVEIFC_HH__ 4114039Sstacze01@arm.com#define __DEV_ARM_SMMU_V3_SLAVEIFC_HH__ 4214039Sstacze01@arm.com 4314039Sstacze01@arm.com#include <list> 4414039Sstacze01@arm.com 4514039Sstacze01@arm.com#include "dev/arm/smmu_v3_caches.hh" 4614039Sstacze01@arm.com#include "dev/arm/smmu_v3_defs.hh" 4714039Sstacze01@arm.com#include "dev/arm/smmu_v3_events.hh" 4814039Sstacze01@arm.com#include "dev/arm/smmu_v3_ports.hh" 4914039Sstacze01@arm.com#include "dev/arm/smmu_v3_proc.hh" 5014039Sstacze01@arm.com#include "params/SMMUv3SlaveInterface.hh" 5114252Sgabeblack@google.com#include "sim/clocked_object.hh" 5214039Sstacze01@arm.com 5314039Sstacze01@arm.comclass SMMUTranslationProcess; 5414039Sstacze01@arm.comclass SMMUv3; 5514039Sstacze01@arm.comclass SMMUSlavePort; 5614039Sstacze01@arm.com 5714252Sgabeblack@google.comclass SMMUv3SlaveInterface : public ClockedObject 5814039Sstacze01@arm.com{ 5914064Sadrian.herrera@arm.com protected: 6014064Sadrian.herrera@arm.com friend class SMMUTranslationProcess; 6114064Sadrian.herrera@arm.com 6214039Sstacze01@arm.com public: 6314039Sstacze01@arm.com SMMUv3 *smmu; 6414039Sstacze01@arm.com SMMUTLB* microTLB; 6514039Sstacze01@arm.com SMMUTLB* mainTLB; 6614039Sstacze01@arm.com 6714039Sstacze01@arm.com const bool microTLBEnable; 6814039Sstacze01@arm.com const bool mainTLBEnable; 6914039Sstacze01@arm.com 7014039Sstacze01@arm.com SMMUSemaphore slavePortSem; 7114039Sstacze01@arm.com SMMUSemaphore microTLBSem; 7214039Sstacze01@arm.com SMMUSemaphore mainTLBSem; 7314039Sstacze01@arm.com 7414039Sstacze01@arm.com const Cycles microTLBLat; 7514039Sstacze01@arm.com const Cycles mainTLBLat; 7614039Sstacze01@arm.com 7714039Sstacze01@arm.com SMMUSlavePort *slavePort; 7814039Sstacze01@arm.com SMMUATSSlavePort atsSlavePort; 7914039Sstacze01@arm.com SMMUATSMasterPort atsMasterPort; 8014039Sstacze01@arm.com 8114039Sstacze01@arm.com // in bytes 8214039Sstacze01@arm.com const unsigned portWidth; 8314039Sstacze01@arm.com 8414039Sstacze01@arm.com unsigned wrBufSlotsRemaining; 8514039Sstacze01@arm.com unsigned xlateSlotsRemaining; 8614223Sgiacomo.travaglini@arm.com unsigned pendingMemAccesses; 8714039Sstacze01@arm.com 8814039Sstacze01@arm.com const bool prefetchEnable; 8914039Sstacze01@arm.com const bool prefetchReserveLastWay; 9014039Sstacze01@arm.com 9114039Sstacze01@arm.com std::list<SMMUTranslationProcess *> duplicateReqs; 9214039Sstacze01@arm.com SMMUSignal duplicateReqRemoved; 9314039Sstacze01@arm.com 9414039Sstacze01@arm.com std::list<SMMUTranslationProcess *> dependentReads[SMMU_MAX_TRANS_ID]; 9514039Sstacze01@arm.com std::list<SMMUTranslationProcess *> dependentWrites[SMMU_MAX_TRANS_ID]; 9614039Sstacze01@arm.com SMMUSignal dependentReqRemoved; 9714039Sstacze01@arm.com 9814039Sstacze01@arm.com // Receiving translation requests from the master device 9914039Sstacze01@arm.com Tick recvAtomic(PacketPtr pkt); 10014039Sstacze01@arm.com bool recvTimingReq(PacketPtr pkt); 10114039Sstacze01@arm.com void schedTimingResp(PacketPtr pkt); 10214039Sstacze01@arm.com 10314039Sstacze01@arm.com Tick atsSlaveRecvAtomic(PacketPtr pkt); 10414039Sstacze01@arm.com bool atsSlaveRecvTimingReq(PacketPtr pkt); 10514039Sstacze01@arm.com bool atsMasterRecvTimingResp(PacketPtr pkt); 10614039Sstacze01@arm.com void schedAtsTimingResp(PacketPtr pkt); 10714039Sstacze01@arm.com 10814039Sstacze01@arm.com void scheduleDeviceRetry(); 10914039Sstacze01@arm.com void sendDeviceRetry(); 11014039Sstacze01@arm.com void atsSendDeviceRetry(); 11114039Sstacze01@arm.com 11214039Sstacze01@arm.com bool deviceNeedsRetry; 11314039Sstacze01@arm.com bool atsDeviceNeedsRetry; 11414039Sstacze01@arm.com 11514039Sstacze01@arm.com SMMUDeviceRetryEvent sendDeviceRetryEvent; 11614039Sstacze01@arm.com EventWrapper< 11714039Sstacze01@arm.com SMMUv3SlaveInterface, 11814039Sstacze01@arm.com &SMMUv3SlaveInterface::atsSendDeviceRetry> atsSendDeviceRetryEvent; 11914039Sstacze01@arm.com 12014092Smatteo.andreozzi@arm.com Port& getPort(const std::string &name, PortID id) override; 12114039Sstacze01@arm.com 12214039Sstacze01@arm.com public: 12314039Sstacze01@arm.com SMMUv3SlaveInterface(const SMMUv3SlaveInterfaceParams *p); 12414039Sstacze01@arm.com 12514039Sstacze01@arm.com ~SMMUv3SlaveInterface() 12614039Sstacze01@arm.com { 12714039Sstacze01@arm.com delete microTLB; 12814039Sstacze01@arm.com delete mainTLB; 12914039Sstacze01@arm.com } 13014039Sstacze01@arm.com 13114064Sadrian.herrera@arm.com const SMMUv3SlaveInterfaceParams * 13214064Sadrian.herrera@arm.com params() const 13314064Sadrian.herrera@arm.com { 13414064Sadrian.herrera@arm.com return static_cast<const SMMUv3SlaveInterfaceParams *>(_params); 13514064Sadrian.herrera@arm.com } 13614064Sadrian.herrera@arm.com 13714064Sadrian.herrera@arm.com DrainState drain() override; 13814064Sadrian.herrera@arm.com 13914039Sstacze01@arm.com void setSMMU(SMMUv3 *_smmu) { smmu = _smmu; } 14014039Sstacze01@arm.com void sendRange(); 14114039Sstacze01@arm.com}; 14214039Sstacze01@arm.com 14314039Sstacze01@arm.com#endif /* __DEV_ARM_SMMU_V3_SLAVEIFC_HH__ */ 144