Searched refs:recvTimingResp (Results 1 - 25 of 81) sorted by relevance

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/gem5/src/dev/arm/
H A Dsmmu_v3_ports.hh54 virtual bool recvTimingResp(PacketPtr pkt);
68 virtual bool recvTimingResp(PacketPtr pkt);
118 virtual bool recvTimingResp(PacketPtr pkt);
H A Dsmmu_v3_ports.cc52 SMMUMasterPort::recvTimingResp(PacketPtr pkt) function in class:SMMUMasterPort
70 SMMUMasterTableWalkPort::recvTimingResp(PacketPtr pkt) function in class:SMMUMasterTableWalkPort
150 SMMUATSMasterPort::recvTimingResp(PacketPtr pkt) function in class:SMMUATSMasterPort
/gem5/src/mem/
H A Dnoncoherent_xbar.hh160 recvTimingResp(PacketPtr pkt) override
162 return xbar.recvTimingResp(pkt, id);
179 virtual bool recvTimingResp(PacketPtr pkt, PortID master_port_id);
H A Daddr_mapper.hh124 bool recvTimingResp(PacketPtr pkt) function in class:AddrMapper::MapperMasterPort
126 return mapper.recvTimingResp(pkt);
218 bool recvTimingResp(PacketPtr pkt);
H A Dmem_checker_monitor.hh116 bool recvTimingResp(PacketPtr pkt) function in class:MemCheckerMonitor::MonitorMasterPort
118 return mon.recvTimingResp(pkt);
216 bool recvTimingResp(PacketPtr pkt);
H A Dcomm_monitor.hh146 bool recvTimingResp(PacketPtr pkt) function in class:CommMonitor::MonitorMasterPort
148 return mon.recvTimingResp(pkt);
256 bool recvTimingResp(PacketPtr pkt);
H A Dcoherent_xbar.hh178 recvTimingResp(PacketPtr pkt) override
180 return xbar.recvTimingResp(pkt, id);
246 recvTimingResp(PacketPtr pkt) override
303 bool recvTimingResp(PacketPtr pkt, PortID master_port_id);
/gem5/src/mem/ruby/system/
H A DRubyPort.hh71 bool recvTimingResp(PacketPtr pkt);
115 bool recvTimingResp(PacketPtr pkt);
183 bool recvTimingResp(PacketPtr pkt, PortID master_port_id);
/gem5/src/systemc/tlm_bridge/
H A Dtlm_to_gem5.hh101 recvTimingResp(PacketPtr pkt) override
103 return bridge.recvTimingResp(pkt);
159 bool recvTimingResp(PacketPtr pkt);
/gem5/src/mem/protocol/
H A Dtiming.cc84 return peer->recvTimingResp(pkt);
H A Dtiming.hh105 virtual bool recvTimingResp(PacketPtr pkt) = 0;
184 * protocol (causing recvTimingResp to be called on the peer)
/gem5/src/cpu/minor/
H A Dfetch1.hh77 bool recvTimingResp(PacketPtr pkt) function in class:Minor::Fetch1::IcachePort
78 { return fetch.recvTimingResp(pkt); }
381 virtual bool recvTimingResp(PacketPtr pkt);
/gem5/src/cpu/testers/traffic_gen/
H A Dbase.hh99 bool recvTimingResp(PacketPtr pkt);
142 bool recvTimingResp(PacketPtr pkt) function in class:BaseTrafficGen::TrafficGenPort
143 { return trafficGen.recvTimingResp(pkt); }
/gem5/ext/sst/
H A DExtMaster.hh97 bool recvTimingResp(PacketPtr);
/gem5/src/cpu/testers/memtest/
H A Dmemtest.hh110 bool recvTimingResp(PacketPtr pkt);
/gem5/src/cpu/testers/directedtest/
H A DRubyDirectedTester.hh62 virtual bool recvTimingResp(PacketPtr pkt);
H A DRubyDirectedTester.cc97 RubyDirectedTester::CpuPort::recvTimingResp(PacketPtr pkt) function in class:RubyDirectedTester::CpuPort
/gem5/src/cpu/testers/garnet_synthetic_traffic/
H A DGarnetSyntheticTraffic.hh91 virtual bool recvTimingResp(PacketPtr pkt);
/gem5/src/mem/cache/
H A Dnoncoherent_cache.hh91 void recvTimingResp(PacketPtr pkt) override;
/gem5/src/learning_gem5/part2/
H A Dsimple_memobj.hh125 * slave port (causing recvTimingResp to be called on the master
164 bool recvTimingResp(PacketPtr pkt) override;
/gem5/src/mem/ruby/slicc_interface/
H A DAbstractController.cc256 recvTimingResp(pkt);
280 recvTimingResp(pkt);
328 AbstractController::recvTimingResp(PacketPtr pkt) function in class:AbstractController
374 AbstractController::MemoryPort::recvTimingResp(PacketPtr pkt) function in class:AbstractController::MemoryPort
376 controller->recvTimingResp(pkt);
H A DAbstractController.hh144 void recvTimingResp(PacketPtr pkt);
250 bool recvTimingResp(PacketPtr pkt);
/gem5/src/arch/x86/
H A Dpagetable_walker.hh72 bool recvTimingResp(PacketPtr pkt);
187 bool recvTimingResp(PacketPtr pkt);
/gem5/util/tlm/src/
H A Dsc_master_port.hh118 bool recvTimingResp(PacketPtr pkt);
/gem5/src/cpu/testers/rubytest/
H A DRubyTester.hh81 virtual bool recvTimingResp(PacketPtr pkt);

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