/gem5/src/mem/ |
H A D | port.cc | 57 MasterPort::MasterPort(const std::string& name, SimObject* _owner, PortID _id) function in class:MasterPort 62 MasterPort::~MasterPort() 67 MasterPort::bind(Port &peer) 82 MasterPort::unbind() 93 MasterPort::getAddrRanges() const 99 MasterPort::printAddr(Addr a) 132 SlavePort::slaveBind(MasterPort& master_port)
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H A D | MemChecker.py | 51 master = MasterPort("Master port") 54 mem_side = MasterPort("Alias for master")
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H A D | port.hh | 66 * A MasterPort is a specialisation of a BaseMasterPort, which 75 class MasterPort : public Port, public AtomicRequestProtocol, class in inherits:Port,AtomicRequestProtocol,TimingRequestProtocol,FunctionalRequestProtocol 87 MasterPort(const std::string& name, SimObject* _owner, 89 virtual ~MasterPort(); 261 friend class MasterPort; 264 MasterPort* _masterPort; 406 void slaveBind(MasterPort& master_port); 427 MasterPort::sendAtomic(PacketPtr pkt) 433 MasterPort::sendAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &backdoor) 439 MasterPort [all...] |
H A D | Bridge.py | 49 master = MasterPort('Master port')
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H A D | AddrMapper.py | 53 master = MasterPort("Master port")
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H A D | ExternalMaster.py | 48 port = MasterPort("Master port")
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H A D | MemDelay.py | 46 master = MasterPort("Master port")
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H A D | xbar.hh | 175 * individual layers. Note that for a MasterPort, there is 241 class ReqLayer : public Layer<SlavePort, MasterPort> 251 ReqLayer(MasterPort& _port, BaseXBar& _xbar, const std::string& _name) : 263 class RespLayer : public Layer<MasterPort, SlavePort> 280 sendRetry(MasterPort* retry_port) override 286 class SnoopRespLayer : public Layer<SlavePort, MasterPort> 296 SnoopRespLayer(MasterPort& _port, BaseXBar& _xbar, 381 std::vector<MasterPort*> masterPorts;
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H A D | packet_queue.hh | 230 MasterPort& masterPort; 234 static const std::string name(const MasterPort& masterPort, 249 ReqPacketQueue(EventManager& _em, MasterPort& _masterPort, 266 MasterPort& masterPort; 270 static const std::string name(const MasterPort& masterPort, 286 SnoopRespPacketQueue(EventManager& _em, MasterPort& _masterPort,
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H A D | external_master.hh | 55 * presentation of the MasterPort which can be bound. 57 * The external port must provide a gem5 MasterPort interface. 71 class ExternalPort : public MasterPort 79 MasterPort(name_, &owner_), owner(owner_) 90 * external port from gem5 and provide gem5 with a MasterPort that can be
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H A D | SerialLink.py | 54 master = MasterPort('Master port')
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H A D | fs_translating_port_proxy.hh | 84 FSTranslatingPortProxy(MasterPort &port,
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H A D | mem_delay.cc | 82 MemDelay::MasterPort::MasterPort(const std::string &_name, MemDelay &_parent) function in class:MemDelay::MasterPort 90 MemDelay::MasterPort::recvTimingResp(PacketPtr pkt) 100 MemDelay::MasterPort::recvFunctionalSnoop(PacketPtr pkt) 110 MemDelay::MasterPort::recvAtomicSnoop(PacketPtr pkt) 118 MemDelay::MasterPort::recvTimingSnoopReq(PacketPtr pkt)
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H A D | mem_delay.hh | 76 class MasterPort : public QueuedMasterPort class in class:MemDelay 79 MasterPort(const std::string &_name, MemDelay &_parent); 127 MasterPort masterPort;
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/gem5/src/cpu/simple/ |
H A D | noncaching.hh | 58 Tick sendPacket(MasterPort &port, const PacketPtr &pkt) override;
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H A D | noncaching.cc | 57 NonCachingSimpleCPU::sendPacket(MasterPort &port, const PacketPtr &pkt)
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/gem5/src/arch/generic/ |
H A D | BaseTLB.py | 40 master = MasterPort("Port closer to memory side")
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/gem5/src/learning_gem5/part2/ |
H A D | SimpleMemobj.py | 39 mem_side = MasterPort("Memory side port, sends requests")
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H A D | SimpleCache.py | 41 mem_side = MasterPort("Memory side port, sends requests")
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/gem5/src/cpu/testers/rubytest/ |
H A D | RubyTester.hh | 60 class CpuPort : public MasterPort 76 : MasterPort(_name, _tester, _id), tester(_tester), 104 MasterPort* getReadableCpuPort(int idx); 105 MasterPort* getWritableCpuPort(int idx); 140 std::vector<MasterPort*> writePorts; 141 std::vector<MasterPort*> readPorts;
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/gem5/src/cpu/testers/directedtest/ |
H A D | RubyDirectedTester.hh | 50 class CpuPort : public MasterPort 58 : MasterPort(_name, _tester, _id), tester(_tester) 74 MasterPort* getCpuPort(int idx); 101 std::vector<MasterPort*> ports;
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/gem5/src/dev/x86/ |
H A D | I82094AA.py | 39 int_master = MasterPort("Port for sending interrupt messages")
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/gem5/src/mem/ruby/network/ |
H A D | MessageBuffer.py | 45 master = MasterPort("Master port to MessageBuffer receiver")
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/gem5/src/arch/x86/ |
H A D | X86TLB.py | 48 port = MasterPort("Port for the hardware table walker")
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H A D | X86LocalApic.py | 52 int_master = MasterPort("Port for sending interrupt messages")
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