/gem5/src/arch/x86/ |
H A D | vtophys.cc | 63 Walker *walker = dynamic_cast<TLB *>(tc->getDTBPtr())->getWalker(); local 66 Fault fault = walker->startFunctional(
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H A D | X86TLB.py | 48 port = MasterPort("Port for the hardware table walker") 58 walker = Param.X86PagetableWalker(\ 59 X86PagetableWalker(), "page table walker") variable in class:X86TLB
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H A D | pagetable_walker.hh | 66 MasterPort(_name, _walker), walker(_walker) 70 Walker *walker; member in class:X86ISA::Walker::WalkerPort 96 Walker *walker; member in class:X86ISA::Walker::WalkerState 118 walker(_walker), req(_req), state(Ready), 136 std::string name() const {return walker->name();} 147 // State for timing and atomic accesses (need multiple per walker in 150 // State for functional accesses (only need one of these per walker)
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H A D | pagetable_walker.cc | 105 return walker->recvTimingResp(pkt); 139 walker->recvReqRetry(); 241 walker->port.sendAtomic(read); 248 walker->port.sendAtomic(write); 265 walker->port.sendFunctional(read); 511 panic("Unknown page table walker state %d!\n"); 516 walker->tlb->insert(entry.vaddr, entry); 524 nextRead, oldRead->getSize(), flags, walker->masterId); 593 topAddr, dataSize, flags, walker->masterId); 644 Fault fault = walker [all...] |
H A D | tlb.cc | 74 walker = p->walker; 75 walker->setTLB(this); 352 Fault fault = walker->start(tc, translation, req, mode); 453 return walker; 519 return &walker->getPort("port");
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H A D | tlb.hh | 82 Walker * walker; member in class:X86ISA::TLB 159 * Get the table walker port. This is used for 161 * call. For architectures that do not have a table walker, 166 * @return A pointer to the walker port
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H A D | remote_gdb.cc | 75 Walker *walker = dynamic_cast<TLB *>( local 78 Fault fault = walker->startFunctional(context(), va, logBytes, 87 fault = walker->startFunctional(context(), endVa, logBytes,
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/gem5/src/arch/arm/ |
H A D | ArmTLB.py | 69 walker = Param.ArmTableWalker(ArmTableWalker(), "HW Table walker") variable in class:ArmTLB 78 walker = ArmStage2TableWalker() variable in class:ArmStage2TLB
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H A D | tlb.cc | 79 directToStage2(false), tableWalker(p->walker), stage2Tlb(NULL), 1491 // re-retreaving in table walker for speed 1492 DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d:%d)\n",
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/gem5/tests/configs/ |
H A D | pc-simple-timing-ruby.py | 85 cpu.itb.walker.port = system.ruby._cpu_ports[i].slave 86 cpu.dtb.walker.port = system.ruby._cpu_ports[i].slave
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/gem5/src/gpu-compute/ |
H A D | X86GPUTLB.py | 45 port = SlavePort("Port for the hardware table walker") 56 walker = Param.X86PagetableWalker(X86PagetableWalker(), variable in class:X86GPUTLB 57 "page table walker")
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H A D | gpu_tlb.hh | 126 Walker *walker; member in class:X86ISA::GpuTLB
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H A D | gpu_tlb.cc | 930 return walker;
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/gem5/configs/learning_gem5/part3/ |
H A D | msi_caches.py | 118 cpu.itb.walker.port = self.sequencers[i].slave 119 cpu.dtb.walker.port = self.sequencers[i].slave
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H A D | ruby_caches_MI_example.py | 116 cpu.itb.walker.port = self.sequencers[i].slave 117 cpu.dtb.walker.port = self.sequencers[i].slave
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/gem5/configs/example/ |
H A D | se.py | 270 system.cpu[i].itb.walker.port = ruby_port.slave 271 system.cpu[i].dtb.walker.port = ruby_port.slave
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H A D | fs.py | 175 cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave 176 cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
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H A D | apu_se.py | 468 system.cpu[i].itb.walker.port = ruby_port.slave 469 system.cpu[i].dtb.walker.port = ruby_port.slave
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/gem5/src/cpu/ |
H A D | BaseCPU.py | 217 _cached_ports += ["itb.walker.port", "dtb.walker.port"] 255 self.itb.walker.port = iwc.cpu_side 256 self.dtb.walker.port = dwc.cpu_side 260 self._cached_ports += ["itb.walker.port", "dtb.walker.port"] 265 self._cached_ports += ["checker.itb.walker.port", \ 266 "checker.dtb.walker.port"]
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