| /gem5/src/sim/ |
| H A D | global_event.cc | 97 void BaseGlobalEvent::reschedule(Tick when) function in class:BaseGlobalEvent
104 mainEventQueue[i]->reschedule(barrierEvent[i], when);
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| H A D | eventq_impl.hh | 87 EventQueue::reschedule(Event *event, Tick when, bool always) function in class:EventQueue
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| H A D | simulate.cc | 114 simulate_limit_event->reschedule(num_cycles);
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| H A D | eventq.hh | 623 void reschedule(Event *event, Tick when, bool always = false);
708 * parent objects need to reschedule events themselves. This
756 reschedule(Event &event, Tick when, bool always = false) function in class:EventManager
758 eventq->reschedule(&event, when, always);
774 reschedule(Event *event, Tick when, bool always = false) function in class:EventManager
776 eventq->reschedule(event, when, always);
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| H A D | global_event.hh | 145 void reschedule(Tick when);
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| H A D | stat_control.cc | 297 // shift by curTick() and reschedule
299 dumpEvent->reschedule(_when + curTick());
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| /gem5/src/dev/storage/ |
| H A D | ide_disk.cc | 1083 Tick reschedule = 0; local
1089 reschedule = dmaTransferEvent.when();
1094 reschedule = dmaReadWaitEvent.when();
1099 reschedule = dmaWriteWaitEvent.when();
1104 reschedule = dmaPrdReadEvent.when();
1109 reschedule = dmaReadEvent.when();
1114 reschedule = dmaWriteEvent.when();
1121 SERIALIZE_SCALAR(reschedule);
1161 Tick reschedule = 0; local
1164 UNSERIALIZE_SCALAR(reschedule);
[all...] |
| /gem5/src/cpu/testers/memtest/ |
| H A D | memtest.cc | 194 reschedule(noResponseEvent, clockEdge(progressCheck));
305 reschedule(noRequestEvent, clockEdge(progressCheck), true);
337 reschedule(noRequestEvent, clockEdge(progressCheck), true);
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| /gem5/src/cpu/o3/ |
| H A D | mem_dep_unit.hh | 136 void reschedule(const DynInstPtr &inst);
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| H A D | mem_dep_unit_impl.hh | 379 MemDepUnit<MemDepPred, Impl>::reschedule(const DynInstPtr &inst) function in class:MemDepUnit
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| H A D | cpu.hh | 146 reschedule(tickEvent, clockEdge(delay));
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| H A D | inst_queue_impl.hh | 1117 memDepUnit[resched_inst->threadNumber].reschedule(resched_inst);
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| /gem5/src/python/pybind11/ |
| H A D | event.cc | 126 .def("reschedule", &EventQueue::reschedule,
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| /gem5/src/mem/ |
| H A D | packet_queue.cc | 175 em.reschedule(&sendEvent, when);
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| H A D | simple_mem.cc | 220 reschedule(dequeueEvent,
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| H A D | dram_ctrl.cc | 1051 reschedule(rank_ref.activateEvent, act_tick);
1098 reschedule(rank_ref.prechargeEvent, pre_done_at);
1586 reschedule(dram_pkt->rankRef.writeDoneEvent, dram_pkt->readyTime);
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| /gem5/src/arch/x86/ |
| H A D | interrupts.cc | 574 reschedule(apicTimerEvent,
579 reschedule(apicTimerEvent,
769 reschedule(apicTimerEvent, apicTimerEventTick, true);
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| /gem5/src/dev/arm/ |
| H A D | flash_device.cc | 271 reschedule(planeEvent,
338 reschedule(planeEvent, planeEventQueue[next_event].front().time, true);
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| /gem5/src/dev/serial/ |
| H A D | uart8250.cc | 85 reschedule(event, curTick() + interval);
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| /gem5/src/cpu/ |
| H A D | thread_context.cc | 156 cpu->reschedule(quiesceEvent, resume, true);
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| /gem5/src/dev/net/ |
| H A D | dist_iface.cc | 358 reschedule(DistIface::sync->nextAt);
490 eventManager->reschedule(recvDone, curTick());
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| H A D | etherswitch.cc | 177 parent->reschedule(txEvent, curTick() + switchingDelay(), true);
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| /gem5/src/cpu/testers/traffic_gen/ |
| H A D | base.cc | 172 reschedule(noProgressEvent, curTick() + progressCheck, true);
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| /gem5/src/cpu/simple/ |
| H A D | atomic.cc | 768 reschedule(tickEvent, curTick() + latency, true);
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| /gem5/src/cpu/trace/ |
| H A D | trace_cpu.cc | 792 // have its execute tick earlier. Therefore, attempt to reschedule. It
1211 reschedule(dcacheNextEvent, when);
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