| /gem5/src/mem/ |
| H A D | hmc_controller.hh | 90 virtual bool recvTimingReq(PacketPtr pkt, PortID slave_port_id);
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| H A D | tport.hh | 59 * recvFunctional and recvTimingReq through recvAtomic. It is always a
81 bool recvTimingReq(PacketPtr pkt);
95 * hold responses, and implements recvTimingReq and recvFunctional
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| H A D | noncoherent_xbar.hh | 108 recvTimingReq(PacketPtr pkt) override
110 return xbar.recvTimingReq(pkt, id);
178 virtual bool recvTimingReq(PacketPtr pkt, PortID slave_port_id);
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| H A D | tport.cc | 63 SimpleTimingPort::recvTimingReq(PacketPtr pkt) function in class:SimpleTimingPort
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| H A D | dramsim2.hh | 81 bool recvTimingReq(PacketPtr pkt);
204 bool recvTimingReq(PacketPtr pkt);
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| H A D | simple_mem.hh | 98 bool recvTimingReq(PacketPtr pkt) override;
191 bool recvTimingReq(PacketPtr pkt);
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| H A D | addr_mapper.hh | 179 bool recvTimingReq(PacketPtr pkt) function in class:AddrMapper::MapperSlavePort
181 return mapper.recvTimingReq(pkt);
216 bool recvTimingReq(PacketPtr pkt);
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| H A D | mem_checker_monitor.hh | 177 bool recvTimingReq(PacketPtr pkt) function in class:MemCheckerMonitor::MonitorSlavePort
179 return mon.recvTimingReq(pkt);
214 bool recvTimingReq(PacketPtr pkt);
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| H A D | simple_mem.cc | 112 SimpleMemory::recvTimingReq(PacketPtr pkt) function in class:SimpleMemory
298 SimpleMemory::MemoryPort::recvTimingReq(PacketPtr pkt) function in class:SimpleMemory::MemoryPort
300 return memory.recvTimingReq(pkt);
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| H A D | comm_monitor.hh | 212 bool recvTimingReq(PacketPtr pkt) function in class:CommMonitor::MonitorSlavePort
214 return mon.recvTimingReq(pkt);
254 bool recvTimingReq(PacketPtr pkt);
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| H A D | external_slave.cc | 76 bool recvTimingReq(PacketPtr packet);
135 StubSlavePort::recvTimingReq(PacketPtr packet) function in class:StubSlavePort
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| H A D | hmc_controller.cc | 42 bool HMCController::recvTimingReq(PacketPtr pkt, PortID slave_port_id) function in class:HMCController
57 DPRINTF(HMCController, "recvTimingReq: src %s %s 0x%x BUSY\n",
62 DPRINTF(HMCController, "recvTimingReq: src %s %s 0x%x\n",
91 DPRINTF(HMCController, "recvTimingReq: src %s %s 0x%x RETRY\n",
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| /gem5/src/mem/qos/ |
| H A D | mem_sink.hh | 107 bool recvTimingReq(PacketPtr pkt);
239 bool recvTimingReq(PacketPtr pkt);
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| /gem5/src/dev/arm/ |
| H A D | smmu_v3_ports.cc | 104 SMMUSlavePort::recvTimingReq(PacketPtr pkt) function in class:SMMUSlavePort
106 return ifc.recvTimingReq(pkt);
175 SMMUATSSlavePort::recvTimingReq(PacketPtr pkt) function in class:SMMUATSSlavePort
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| H A D | smmu_v3_ports.hh | 84 virtual bool recvTimingReq(PacketPtr pkt);
133 virtual bool recvTimingReq(PacketPtr pkt);
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| H A D | smmu_v3_slaveifc.hh | 100 bool recvTimingReq(PacketPtr pkt);
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| /gem5/src/systemc/tlm_bridge/ |
| H A D | gem5_to_tlm.hh | 119 recvTimingReq(PacketPtr pkt) override
121 return bridge.recvTimingReq(pkt);
180 bool recvTimingReq(PacketPtr packet);
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| /gem5/src/mem/protocol/ |
| H A D | timing.cc | 53 return peer->recvTimingReq(pkt);
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| H A D | timing.hh | 114 * recvTimingReq to be called on the peer) and was unsuccessful.
170 virtual bool recvTimingReq(PacketPtr pkt) = 0;
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| /gem5/src/mem/ruby/system/ |
| H A D | RubyPort.hh | 90 bool recvTimingReq(PacketPtr pkt);
128 bool recvTimingReq(PacketPtr pkt);
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| /gem5/ext/sst/ |
| H A D | ExtSlave.hh | 74 bool recvTimingReq(PacketPtr packet);
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| /gem5/util/tlm/src/ |
| H A D | sc_slave_port.hh | 101 bool recvTimingReq(PacketPtr packet);
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| /gem5/src/mem/cache/ |
| H A D | noncoherent_cache.hh | 81 void recvTimingReq(PacketPtr pkt) override;
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| H A D | cache.hh | 100 void recvTimingReq(PacketPtr pkt) override;
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| /gem5/src/learning_gem5/part2/ |
| H A D | simple_memobj.hh | 121 bool recvTimingReq(PacketPtr pkt) override;
168 * master port (causing recvTimingReq to be called on the slave
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