Searched refs:port_data (Results 1 - 19 of 19) sorted by relevance

/gem5/src/mem/
H A DExternalMaster.py52 port_data = Param.String('stub', 'A string to pass to the port' variable in class:ExternalMaster
H A DExternalSlave.py52 port_data = Param.String('stub', 'A string to pass to the port' variable in class:ExternalSlave
H A Dexternal_master.hh51 * port_data parameter of the port which can be used to identify the external
99 const std::string &port_data) = 0;
H A Dexternal_slave.hh49 * port_data parameter of the port which can be used to identify the external
101 const std::string &port_data) = 0;
H A Dexternal_slave.cc89 const std::string &port_data)
93 DPRINTF(ExternalPort, "finding stub port '%s'\n", port_data);
188 portData(params->port_data),
214 " port_data: '%s'\n", portName, portType, portData);
86 getExternalPort( const std::string &name_, ExternalSlave &owner, const std::string &port_data) argument
H A Dexternal_master.cc59 portData(params->port_data),
81 " port_data: '%s'\n", portName, portType, portData);
/gem5/ext/sst/
H A Dgem5.hh88 const std::string &port_data);
92 const std::string &port_data);
H A Dgem5.cc253 ExternalMaster &owner, const std::string &port_data)
263 ExternalSlave &owner, const std::string &port_data)
252 getExternalPort(const std::string &name, ExternalMaster &owner, const std::string &port_data) argument
262 getExternalPort(const std::string &name, ExternalSlave &owner, const std::string &port_data) argument
/gem5/util/tlm/conf/
H A Dtlm_master.py64 system.tlm.port_data = "transactor"
H A Dtlm_slave.py67 system.tlm.port_data = "transactor"
H A Dtlm_elastic_slave.py110 system.tlm.port_data = "transactor"
/gem5/util/tlm/src/
H A Dsc_slave_port.hh133 const std::string &port_data);
H A Dsc_master_port.hh156 const std::string &port_data);
H A Dsc_slave_port.cc390 const std::string &port_data)
393 auto* port = new SCSlavePort(name, port_data, owner);
395 control.registerSlavePort(port_data, port);
388 getExternalPort(const std::string &name, ExternalSlave &owner, const std::string &port_data) argument
H A Dsc_master_port.cc418 const std::string &port_data)
421 auto* port = new SCMasterPort(name, port_data, owner, control);
423 control.registerMasterPort(port_data, port);
416 getExternalPort(const std::string &name, ExternalMaster &owner, const std::string &port_data) argument
/gem5/configs/common/
H A DMemConfig.py182 port_data=opt_tlm_memory,
191 port_data="init_mem0", port=xbar.master,
H A DCacheConfig.py224 return ExternalCache(port_data=name, port_type=port_type,
H A DFSConfig.py350 self.external_io = ExternalMaster(port_data="external_io",
355 self.iocache = ExternalSlave(port_data="iocache",
/gem5/util/tlm/examples/
H A Dtlm_elastic_slave_with_l2.py118 system.tlm.port_data = "transactor1"

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