Searched refs:period (Results 1 - 25 of 36) sorted by relevance

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/gem5/src/systemc/tests/systemc/misc/parsing/T_1_1_2_1/
H A DT_1_1_2_1.cpp48 // double period = clock2.period();
49 sc_time period = clock2.period(); local
/gem5/src/python/m5/
H A Devent.py74 def __init__(self, eventq, period):
76 self.period = int(period)
78 self.eventq.schedule(self, m5.curTick() + self.period)
82 self.eventq.schedule(self, m5.curTick() + self.period)
/gem5/src/systemc/channel/
H A Dsc_clock.cc105 sc_clock::sc_clock(const char *name, const sc_time &period, argument
109 _period(period), _dutyCycle(duty_cycle), _startTime(start_time),
112 if (period == SC_ZERO_TIME) {
114 "increase the period: clock '" +
119 if (duty_cycle * period == SC_ZERO_TIME) {
121 "increase the period or increase the duty cycle: clock '" +
126 if (duty_cycle * period == period) {
128 "increase the period or decrease the duty cycle: clock '" +
133 _gem5UpEdge = new ::sc_gem5::ClockTick(this, true, period);
150 sc_clock(const char *name, double period, double duty_cycle, double start_time, bool posedge_first) argument
172 const sc_time &sc_clock::period() const { return _period; } function in class:sc_core::sc_clock
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/gem5/src/sim/
H A Dstat_control.hh84 * @param period The period at which the dumping should occur.
86 void periodicStatDump(Tick period = 0);
H A Dstat_control.cc258 periodicStatDump(Tick period) argument
261 * If the period is set to 0, then we do not want to dump periodically,
262 * thus we deschedule the event. Else, if the period is not 0, but the event
267 if (dumpEvent != NULL && (period == 0 || dumpEvent->scheduled())) {
273 * If the period is not 0, we schedule the event. If this is called with a
274 * period that is less than the current tick, then we shift the first dump
277 if (period != 0) {
279 if (period >= curTick()) {
280 schedStatEvent(true, true, (Tick)period, (Tick)period);
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H A Dpseudo_inst.hh83 void resetstats(ThreadContext *tc, Tick delay, Tick period);
84 void dumpstats(ThreadContext *tc, Tick delay, Tick period);
85 void dumpresetstats(ThreadContext *tc, Tick delay, Tick period);
86 void m5checkpoint(ThreadContext *tc, Tick delay, Tick period);
H A Droot.cc53 Time cur_time, diff, period = timeSyncPeriod(); local
58 Time remainder = period - diff;
59 if (diff < period && remainder > _spinThreshold) {
61 // Sleep until the end of the period, or until a signal.
66 } while (diff < period);
88 /// Configure the period for time sync events.
H A Dpseudo_inst.cc435 resetstats(ThreadContext *tc, Tick delay, Tick period) argument
437 DPRINTF(PseudoInst, "PseudoInst::resetstats(%i, %i)\n", delay, period);
443 Tick repeat = period * SimClock::Int::ns;
449 dumpstats(ThreadContext *tc, Tick delay, Tick period) argument
451 DPRINTF(PseudoInst, "PseudoInst::dumpstats(%i, %i)\n", delay, period);
457 Tick repeat = period * SimClock::Int::ns;
463 dumpresetstats(ThreadContext *tc, Tick delay, Tick period) argument
465 DPRINTF(PseudoInst, "PseudoInst::dumpresetstats(%i, %i)\n", delay, period);
471 Tick repeat = period * SimClock::Int::ns;
477 m5checkpoint(ThreadContext *tc, Tick delay, Tick period) argument
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/gem5/src/dev/arm/
H A Denergy_ctrl.hh169 static uint32_t ticksTokHz(Tick period) { argument
170 return (uint32_t)(SimClock::Int::ms / period);
H A Denergy_ctrl.cc85 Tick period; local
129 period = dvfsHandler->clkPeriodAtPerfLevel(domainID, perfLevelToRead);
130 result = ticksTokHz(period);
/gem5/src/cpu/kvm/
H A Dperfevent.hh80 * Set the initial sample period (overflow count) of an event. If
84 * @param period Number of counter events before the counter
87 PerfKvmCounterConfig &samplePeriod(uint64_t period) { argument
89 attr.sample_period = period;
249 * Update the period of an overflow counter.
252 * like the new period isn't effective until after the next
254 * period, you will see one sample with the old period and then
255 * start sampling with the new period. This problem was fixed for
262 * @param period Overflo
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H A Dperfevent.cc123 PerfKvmCounter::period(uint64_t period) argument
125 if (ioctl(PERF_EVENT_IOC_PERIOD, &period) == -1)
126 panic("KVM: Failed to set period of performance counter (%i)\n", errno);
/gem5/src/systemc/ext/channel/
H A Dsc_clock.hh57 sc_clock(const char *name, const sc_time &period,
69 sc_clock(const char *name, double period, double duty_cycle=0.5,
76 const sc_time &period() const;
/gem5/src/dev/
H A Dintel_8254_timer.cc103 initial_count(0), latched_count(0), period(0), mode(0),
107 offset = period * event.getInterval();
187 period = initial_count - 1;
189 period = initial_count;
191 offset = period * event.getInterval();
193 if (running && (period > 0))
194 event.setTo(period);
236 paramOut(cp, base + ".period", period);
254 paramIn(cp, base + ".period", perio
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H A Dintel_8254_timer.hh126 /** Interrupt period */
127 uint16_t period; member in class:Intel8254Timer::Counter
/gem5/ext/pybind11/include/pybind11/
H A Dchrono.h36 typedef typename type::period period; typedef in class:duration_caster
49 value = type(duration_cast<duration<rep, period>>(
57 value = type(duration_cast<duration<rep, period>>(duration<double>(PyFloat_AsDouble(src.ptr()))));
64 static const std::chrono::duration<rep, period>& get_duration(const std::chrono::duration<rep, period> &src) {
69 template <typename Clock> static std::chrono::duration<rep, period> get_duration(const std::chrono::time_point<Clock, std::chrono::duration<rep, period>> &src) {
/gem5/src/systemc/tests/systemc/compliance_1666/test202/
H A Dtest202.cpp8 // 2) sc_clock - start_time and posedge_first (in addition to period and duty_cycle)
33 sc_assert(clk.period() == sc_time(20, SC_NS));
/gem5/configs/dram/
H A Dlow_power_sweep.py85 help = "time in ps of an idle period at the end ")
133 # generator remains in the state for specific period. This period is 0.25 ms.
135 period = 250000000 variable
191 cfg_file.write("""# STATE state# period mode=DRAM
201 (nxt_state, period, "DRAM", args.rd_perc, max_addr,
207 # State for idle period
235 # every period, dump and reset all stats
236 periodicStatDump(period)
245 m5.simulate(nxt_state * period
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H A Dlat_mem_rd.py218 period = long(itt * (max_range / burst_size)) variable
231 (nxt_state, period, filename))
237 (nxt_state, period, filename))
299 # every period, dump and reset all stats
300 periodicStatDump(period)
307 m5.simulate(nxt_state * period)
H A Dsweep.py135 period = 250000000 variable
137 # stay in each state as long as the dump/reset period, use the entire
177 # every period, dump and reset all stats
178 periodicStatDump(period)
191 yield generator(period,
/gem5/tests/configs/
H A Dswitcheroo.py96 period -- Switching frequency in Hz.
116 # Determine the switching period, this has to be done after
118 period = m5.ticks.fromSeconds(1.0 / freq)
120 exit_event = m5.simulate(period)
/gem5/util/m5/
H A Dlua_gem5Op.c126 uint64_t period = lua_tointeger(L, 2); local
127 m5_checkpoint(delay, period);
144 uint64_t period = lua_tointeger(L, 2); local
145 m5_dump_stats(delay, period);
153 uint64_t period = lua_tointeger(L, 2); local
154 m5_dump_reset_stats(delay, period);
/gem5/src/systemc/tests/systemc/communication/sc_clock/test01/
H A Dtest01.cpp45 cout << "period = " << clk.period() << endl; \
/gem5/src/systemc/core/
H A Dsc_time.cc405 // Shrink the frequency by scaling down the time period, ie converting
412 // Convert the frequency into a period.
413 Tick period; local
416 period = 1000 / frequency;
418 period = frequency;
421 // Scale our integer value by the period.
422 _value = t.value() * period;
/gem5/ext/systemc/src/sysc/communication/
H A Dsc_clock.h92 // get the period
93 const sc_time& period() const function in class:sc_core::sc_clock
156 sc_time m_period; // the period of this clock
157 double m_duty_cycle; // the duty cycle (fraction of period)

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