110396Sakash.bagdia@arm.com/*
210396Sakash.bagdia@arm.com * Copyright (c) 2012-2014 ARM Limited
310396Sakash.bagdia@arm.com * All rights reserved
410396Sakash.bagdia@arm.com *
510396Sakash.bagdia@arm.com * The license below extends only to copyright in the software and shall
610396Sakash.bagdia@arm.com * not be construed as granting a license to any other intellectual
710396Sakash.bagdia@arm.com * property including but not limited to intellectual property relating
810396Sakash.bagdia@arm.com * to a hardware implementation of the functionality of the software
910396Sakash.bagdia@arm.com * licensed hereunder.  You may use the software subject to the license
1010396Sakash.bagdia@arm.com * terms below provided that you ensure that this notice is replicated
1110396Sakash.bagdia@arm.com * unmodified and in its entirety in all distributions of the software,
1210396Sakash.bagdia@arm.com * modified or unmodified, in source code or in binary form.
1310396Sakash.bagdia@arm.com *
1410396Sakash.bagdia@arm.com * Redistribution and use in source and binary forms, with or without
1510396Sakash.bagdia@arm.com * modification, are permitted provided that the following conditions are
1610396Sakash.bagdia@arm.com * met: redistributions of source code must retain the above copyright
1710396Sakash.bagdia@arm.com * notice, this list of conditions and the following disclaimer;
1810396Sakash.bagdia@arm.com * redistributions in binary form must reproduce the above copyright
1910396Sakash.bagdia@arm.com * notice, this list of conditions and the following disclaimer in the
2010396Sakash.bagdia@arm.com * documentation and/or other materials provided with the distribution;
2110396Sakash.bagdia@arm.com * neither the name of the copyright holders nor the names of its
2210396Sakash.bagdia@arm.com * contributors may be used to endorse or promote products derived from
2310396Sakash.bagdia@arm.com * this software without specific prior written permission.
2410396Sakash.bagdia@arm.com *
2510396Sakash.bagdia@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
2610396Sakash.bagdia@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
2710396Sakash.bagdia@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
2810396Sakash.bagdia@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
2910396Sakash.bagdia@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
3010396Sakash.bagdia@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
3110396Sakash.bagdia@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
3210396Sakash.bagdia@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
3310396Sakash.bagdia@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3410396Sakash.bagdia@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
3510396Sakash.bagdia@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3610396Sakash.bagdia@arm.com *
3710396Sakash.bagdia@arm.com * Authors: Vasileios Spiliopoulos
3810396Sakash.bagdia@arm.com *          Akash Bagdia
3910396Sakash.bagdia@arm.com *          Stephan Diestelhorst
4010396Sakash.bagdia@arm.com */
4110396Sakash.bagdia@arm.com
4210396Sakash.bagdia@arm.com/**
4310396Sakash.bagdia@arm.com * @file
4410396Sakash.bagdia@arm.com * The energy controller is a device being used to manage power and energy
4510396Sakash.bagdia@arm.com * related control operations within the system. It provides the necessary
4610396Sakash.bagdia@arm.com * software interface to the kernel. The kernel will require gem5 specific
4710396Sakash.bagdia@arm.com * drivers to access this device.
4810396Sakash.bagdia@arm.com *
4910396Sakash.bagdia@arm.com * Tasks handled by the controller are:
5010396Sakash.bagdia@arm.com * a) Dynamic voltage and frequency scaling control operations
5110396Sakash.bagdia@arm.com *
5210396Sakash.bagdia@arm.com * Note that the registers defined do not resemble any specific controller
5310396Sakash.bagdia@arm.com * device in real hardware. They are currently design to accomodate the gem5
5410396Sakash.bagdia@arm.com * system requirements.
5510396Sakash.bagdia@arm.com */
5610396Sakash.bagdia@arm.com
5710396Sakash.bagdia@arm.com#ifndef __DEV_ARM_ENERGY_CTRL_HH__
5810396Sakash.bagdia@arm.com#define __DEV_ARM_ENERGY_CTRL_HH__
5910396Sakash.bagdia@arm.com
6010396Sakash.bagdia@arm.com#include "dev/io_device.hh"
6110396Sakash.bagdia@arm.com#include "params/EnergyCtrl.hh"
6210396Sakash.bagdia@arm.com
6310396Sakash.bagdia@arm.comclass DVFSHandler;
6410396Sakash.bagdia@arm.com
6510396Sakash.bagdia@arm.comclass EnergyCtrl : public BasicPioDevice
6610396Sakash.bagdia@arm.com{
6710396Sakash.bagdia@arm.com  public:
6810396Sakash.bagdia@arm.com    /**
6910396Sakash.bagdia@arm.com     * Discovery flows:
7010396Sakash.bagdia@arm.com     * ----------------
7110396Sakash.bagdia@arm.com     *   * get basic DVFS handler information
7210396Sakash.bagdia@arm.com     *     read(DVFS_HANDLER_STATUS)
7310396Sakash.bagdia@arm.com     *     read(DVFS_HANDLER_TRANS_LATENCY)
7410396Sakash.bagdia@arm.com     *
7510396Sakash.bagdia@arm.com     *   * get the number of domain IDs
7610396Sakash.bagdia@arm.com     *     read(DVFS_NUM_DOMAINS) -> domains
7710396Sakash.bagdia@arm.com     *
7810396Sakash.bagdia@arm.com     *   * query the driver to get the IDs for all i in domains
7910396Sakash.bagdia@arm.com     *     write(DVFS_DOMAINID_AT_INDEX <- i)
8010396Sakash.bagdia@arm.com     *     read(DOMAIN_ID) -> domainID_i
8110396Sakash.bagdia@arm.com     *
8210396Sakash.bagdia@arm.com     *   * for each domainID i get voltage / frequency pairs
8310396Sakash.bagdia@arm.com     *     write(DOMAIN_ID <- domainID_i)
8410396Sakash.bagdia@arm.com     *     read(NUM_OF_PERF_LEVELS) -> levels_i
8510396Sakash.bagdia@arm.com     *     * for each l in levels_i
8610396Sakash.bagdia@arm.com     *       write(PERF_LEVEL_TO_READ <- l)
8710396Sakash.bagdia@arm.com     *       read(FREQ_AT_PERF_LEVEL) -> freq_l_i
8810396Sakash.bagdia@arm.com     *       read(VOLT_AT_PERF_LEVEL) -> volt_l_i
8910396Sakash.bagdia@arm.com     *
9010396Sakash.bagdia@arm.com     *
9110396Sakash.bagdia@arm.com     * Setting a specific performance level (V/F combination)
9210396Sakash.bagdia@arm.com     * ------------------------------------------------------
9310396Sakash.bagdia@arm.com     *   * get performance for domain_ID i
9410396Sakash.bagdia@arm.com     *     write(DOMAIN_ID <- i)
9510396Sakash.bagdia@arm.com     *     read(PERF_LEVEL) -> perf_level_i
9610396Sakash.bagdia@arm.com     *
9710396Sakash.bagdia@arm.com     *   * set performance for domain_ID i
9810396Sakash.bagdia@arm.com     *     write(DOMAIN_ID <- i)
9910396Sakash.bagdia@arm.com     *     write(PERF_LEVEL <- perf_level_i)
10010396Sakash.bagdia@arm.com     *     * wait for DVFS transition completion
10110396Sakash.bagdia@arm.com     *       while (!read(PERF_LEVEL_ACK));
10210396Sakash.bagdia@arm.com     */
10310396Sakash.bagdia@arm.com
10410396Sakash.bagdia@arm.com    enum Registers {
10510396Sakash.bagdia@arm.com        DVFS_HANDLER_STATUS = 0,
10610396Sakash.bagdia@arm.com        DVFS_NUM_DOMAINS,
10710396Sakash.bagdia@arm.com        DVFS_DOMAINID_AT_INDEX,
10810396Sakash.bagdia@arm.com        DVFS_HANDLER_TRANS_LATENCY,
10910396Sakash.bagdia@arm.com        DOMAIN_ID,
11010396Sakash.bagdia@arm.com        PERF_LEVEL,
11110396Sakash.bagdia@arm.com        PERF_LEVEL_ACK,
11210396Sakash.bagdia@arm.com        NUM_OF_PERF_LEVELS,
11310396Sakash.bagdia@arm.com        PERF_LEVEL_TO_READ,
11410396Sakash.bagdia@arm.com        FREQ_AT_PERF_LEVEL,
11510396Sakash.bagdia@arm.com        VOLT_AT_PERF_LEVEL,
11610396Sakash.bagdia@arm.com        PIO_NUM_FIELDS
11710396Sakash.bagdia@arm.com    };
11810396Sakash.bagdia@arm.com
11910396Sakash.bagdia@arm.com    typedef EnergyCtrlParams Params;
12010396Sakash.bagdia@arm.com    EnergyCtrl(const Params *p);
12110396Sakash.bagdia@arm.com
12210396Sakash.bagdia@arm.com    /**
12310396Sakash.bagdia@arm.com     * Read command sent to the device
12410396Sakash.bagdia@arm.com     * @param pkt Packet describing this request
12510396Sakash.bagdia@arm.com     * @return number of ticks it took to complete
12610396Sakash.bagdia@arm.com     */
12711174Sandreas.hansson@arm.com    Tick read(PacketPtr pkt) override;
12810396Sakash.bagdia@arm.com    /**
12910396Sakash.bagdia@arm.com     * Write command sent to the device
13010396Sakash.bagdia@arm.com     * @param pkt Packet describing this request
13110396Sakash.bagdia@arm.com     * @return number of ticks it took to complete
13210396Sakash.bagdia@arm.com     */
13311174Sandreas.hansson@arm.com    Tick write(PacketPtr pkt) override;
13410396Sakash.bagdia@arm.com
13511168Sandreas.hansson@arm.com    void serialize(CheckpointOut &cp) const override;
13611168Sandreas.hansson@arm.com    void unserialize(CheckpointIn &cp) override;
13710396Sakash.bagdia@arm.com
13811174Sandreas.hansson@arm.com    void startup() override;
13911174Sandreas.hansson@arm.com    void init() override;
14010396Sakash.bagdia@arm.com
14110396Sakash.bagdia@arm.com  private:
14210396Sakash.bagdia@arm.com    DVFSHandler *dvfsHandler;
14310396Sakash.bagdia@arm.com
14410396Sakash.bagdia@arm.com    /**
14510396Sakash.bagdia@arm.com     * Cluster ID (DOMAIN_ID) R/W register, programmed to ID of the domain for
14610396Sakash.bagdia@arm.com     * which the set/get performance level command can be issued
14710396Sakash.bagdia@arm.com     */
14810396Sakash.bagdia@arm.com    uint32_t domainID;
14910396Sakash.bagdia@arm.com
15010396Sakash.bagdia@arm.com    /**
15110396Sakash.bagdia@arm.com     * Index for getting the domain ID from the domain ID list available with
15210396Sakash.bagdia@arm.com     * the DVFS handler
15310396Sakash.bagdia@arm.com     */
15410396Sakash.bagdia@arm.com    uint32_t domainIDIndexToRead;
15510396Sakash.bagdia@arm.com
15610396Sakash.bagdia@arm.com    /**
15710396Sakash.bagdia@arm.com     * Acknowledgment (PERF_LEVEL_ACK) RO register, software polls this
15810396Sakash.bagdia@arm.com     * register to read back the status of the last programmed change in the
15910396Sakash.bagdia@arm.com     * domain ID and/or the performance level. Valid values are:
16010396Sakash.bagdia@arm.com     * '0' - Ack is not OK yet
16110396Sakash.bagdia@arm.com     * '1' - Ack is OK
16210396Sakash.bagdia@arm.com     * It is a read destructive register with a read of '1' resets the ack to
16310396Sakash.bagdia@arm.com     * '0'.
16410396Sakash.bagdia@arm.com     */
16510396Sakash.bagdia@arm.com    uint32_t perfLevelAck;
16610396Sakash.bagdia@arm.com
16710396Sakash.bagdia@arm.com    uint32_t perfLevelToRead;
16810396Sakash.bagdia@arm.com
16910396Sakash.bagdia@arm.com    static uint32_t ticksTokHz(Tick period) {
17010396Sakash.bagdia@arm.com        return (uint32_t)(SimClock::Int::ms / period);
17110396Sakash.bagdia@arm.com    }
17210396Sakash.bagdia@arm.com
17310396Sakash.bagdia@arm.com    static uint32_t toMicroVolt(double voltage) {
17410396Sakash.bagdia@arm.com        return (uint32_t)(voltage * 1000000);
17510396Sakash.bagdia@arm.com    }
17610396Sakash.bagdia@arm.com
17710396Sakash.bagdia@arm.com    /**
17810396Sakash.bagdia@arm.com      * Update the acknowledgment that is read back by the software to confirm
17910396Sakash.bagdia@arm.com      * newly requested performance level has been set.
18010396Sakash.bagdia@arm.com     */
18110396Sakash.bagdia@arm.com    void updatePLAck() {
18210396Sakash.bagdia@arm.com        perfLevelAck = 1;
18310396Sakash.bagdia@arm.com    }
18410396Sakash.bagdia@arm.com
18512086Sspwilson2@wisc.edu    EventFunctionWrapper updateAckEvent;
18610396Sakash.bagdia@arm.com};
18710396Sakash.bagdia@arm.com#endif //__DEV_ARM_ENERGY_CTRL_HH__
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