Searched refs:latency (Results 1 - 25 of 82) sorted by relevance

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/gem5/src/learning_gem5/part2/
H A Dhello_object.cc44 latency(params->time_to_wait),
55 schedule(event, latency);
69 schedule(event, curTick() + latency);
H A Dhello_object.hh58 const Tick latency; member in class:HelloObject
H A DSimpleCache.py43 latency = Param.Cycles(1, "Cycles taken on a hit or to resolve a miss") variable in class:SimpleCache
/gem5/src/mem/
H A DSimpleMemory.py49 latency = Param.Latency('30ns', "Request to response latency") variable in class:SimpleMemory
50 latency_var = Param.Latency('0ns', "Request to response latency variance")
H A Dtport.cc57 // do an atomic access and throw away the returned latency
73 Tick latency = recvAtomic(pkt); local
79 schedTimingResp(pkt, curTick() + latency);
H A Dsnoop_filter.hh137 * @return Pair of a vector of snoop target ports and lookup latency.
160 * latency.
227 std::pair<SnoopList, Cycles> snoopAll(Cycles latency) const
229 return std::make_pair(slavePorts, latency);
232 Cycles latency) const
234 return std::make_pair(slave_ports, latency);
236 std::pair<SnoopList, Cycles> snoopDown(Cycles latency) const
239 return std::make_pair(empty , latency);
/gem5/src/mem/ruby/network/
H A DBasicRouter.py40 latency = Param.Cycles(1, "number of cycles inside router") variable in class:BasicRouter
H A DBasicRouter.cc35 m_latency = p->latency;
H A DBasicLink.py37 latency = Param.Cycles(1, "latency") variable in class:BasicLink
H A DBasicLink.cc34 m_latency = p->latency;
/gem5/src/dev/x86/
H A Di8237.hh43 Tick latency; member in class:X86ISA::I8237
55 I8237(Params *p) : BasicPioDevice(p, 16), latency(p->pio_latency), maskReg(0)
H A Dintdev.hh96 Tick latency; member in class:X86ISA::IntMasterPort
103 device(dev), latency(_latency)
121 schedTimingReq(pkt, curTick() + latency);
124 // ignore the latency involved in the atomic transaction
127 // also ignore the latency in handling the response
141 IntDevice(SimObject * parent, Tick latency = 0) :
142 intMasterPort(parent->name() + ".int_master", parent, this, latency)
H A Dspeaker.hh46 Tick latency; member in class:X86ISA::Speaker
68 latency(p->pio_latency), controlVal(0), timer(p->i8254)
H A Dspeaker.cc53 return latency;
74 return latency;
H A Di8237.cc68 return latency;
126 return latency;
H A Di8254.hh45 Tick latency; member in class:X86ISA::I8254
88 I8254(Params *p) : BasicPioDevice(p, 4), latency(p->pio_latency),
/gem5/src/mem/ruby/network/garnet2.0/
H A DGarnetNetwork.hh114 increment_packet_network_latency(Cycles latency, int vnet) argument
116 m_packet_network_latency[vnet] += latency;
120 increment_packet_queueing_latency(Cycles latency, int vnet) argument
122 m_packet_queueing_latency[vnet] += latency;
129 increment_flit_network_latency(Cycles latency, int vnet) argument
131 m_flit_network_latency[vnet] += latency;
135 increment_flit_queueing_latency(Cycles latency, int vnet) argument
137 m_flit_queueing_latency[vnet] += latency;
/gem5/configs/topologies/
H A DCrossbar.py42 # default values for link latency and router latency.
58 latency = link_latency)
69 latency = link_latency))
77 latency = link_latency))
H A DPt2Pt.py48 # default values for link latency and router latency.
58 routers = [Router(router_id=i, latency = router_latency) \
63 latency = link_latency)
76 latency = link_latency))
H A DCluster.py108 link_out.latency = node.extLatency
109 link_in.latency = node.extLatency
111 link_out.latency = self.intLatency
112 link_in.latency = self.intLatency
125 link.latency = self.intLatency
H A DMeshDirCorners_XY.py55 # default values for link latency and router latency.
86 routers = [Router(router_id=i, latency = router_latency) \
100 latency = link_latency))
127 latency = link_latency))
131 latency = link_latency))
135 latency = link_latency))
139 latency = link_latency))
147 latency = link_latency))
165 latency
[all...]
H A DMesh_westfirst.py63 # default values for link latency and router latency.
76 routers = [Router(router_id=i, latency=router_latency) \
100 latency = link_latency))
110 latency = link_latency))
127 latency = link_latency,
140 latency = link_latency,
154 latency = link_latency,
167 latency = link_latency,
H A DMesh_XY.py61 # default values for link latency and router latency.
75 routers = [Router(router_id=i, latency = router_latency) \
99 latency = link_latency))
109 latency = link_latency))
128 latency = link_latency,
143 latency = link_latency,
158 latency = link_latency,
173 latency = link_latency,
/gem5/tests/gem5/memory/
H A Dsimple-run.py45 parser.add_argument('--latency', default=None)
62 if args.latency:
63 latency = args.latency variable in class:MyMem
/gem5/src/mem/ruby/system/
H A DVIPERCoalescer.cc222 Tick latency = cyclesToTicks( local
224 assert(latency > 0);
225 m_mandatory_q_ptr->enqueue(msg, clockEdge(), latency);
253 Tick latency = cyclesToTicks( local
255 assert(latency > 0);
256 m_mandatory_q_ptr->enqueue(msg, clockEdge(), latency);
281 Tick latency = cyclesToTicks( local
283 assert(latency > 0);
284 m_mandatory_q_ptr->enqueue(msg, clockEdge(), latency);
297 Tick latency local
[all...]

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