111663Stushar@ece.gatech.edu# Copyright (c) 2010 Advanced Micro Devices, Inc. 211663Stushar@ece.gatech.edu# All rights reserved. 311663Stushar@ece.gatech.edu# 411663Stushar@ece.gatech.edu# Redistribution and use in source and binary forms, with or without 511663Stushar@ece.gatech.edu# modification, are permitted provided that the following conditions are 611663Stushar@ece.gatech.edu# met: redistributions of source code must retain the above copyright 711663Stushar@ece.gatech.edu# notice, this list of conditions and the following disclaimer; 811663Stushar@ece.gatech.edu# redistributions in binary form must reproduce the above copyright 911663Stushar@ece.gatech.edu# notice, this list of conditions and the following disclaimer in the 1011663Stushar@ece.gatech.edu# documentation and/or other materials provided with the distribution; 1111663Stushar@ece.gatech.edu# neither the name of the copyright holders nor the names of its 1211663Stushar@ece.gatech.edu# contributors may be used to endorse or promote products derived from 1311663Stushar@ece.gatech.edu# this software without specific prior written permission. 1411663Stushar@ece.gatech.edu# 1511663Stushar@ece.gatech.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1611663Stushar@ece.gatech.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1711663Stushar@ece.gatech.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1811663Stushar@ece.gatech.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 1911663Stushar@ece.gatech.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2011663Stushar@ece.gatech.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2111663Stushar@ece.gatech.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2211663Stushar@ece.gatech.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2311663Stushar@ece.gatech.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2411663Stushar@ece.gatech.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2511663Stushar@ece.gatech.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2611663Stushar@ece.gatech.edu# 2711663Stushar@ece.gatech.edu# Authors: Brad Beckmann 2811663Stushar@ece.gatech.edu 2913774Sandreas.sandberg@arm.comfrom __future__ import print_function 3013774Sandreas.sandberg@arm.comfrom __future__ import absolute_import 3113774Sandreas.sandberg@arm.com 3211663Stushar@ece.gatech.edufrom m5.params import * 3311663Stushar@ece.gatech.edufrom m5.objects import * 3411663Stushar@ece.gatech.edu 3513885Sdavid.hashe@amd.comfrom common import FileSystemConfig 3613885Sdavid.hashe@amd.com 3713774Sandreas.sandberg@arm.comfrom .BaseTopology import SimpleTopology 3811663Stushar@ece.gatech.edu 3911663Stushar@ece.gatech.edu# Creates a Mesh topology with 4 directories, one at each corner. 4011663Stushar@ece.gatech.edu# One L1 (and L2, depending on the protocol) are connected to each router. 4111663Stushar@ece.gatech.edu# XY routing is enforced (using link weights) to guarantee deadlock freedom. 4211663Stushar@ece.gatech.edu 4311663Stushar@ece.gatech.educlass MeshDirCorners_XY(SimpleTopology): 4411663Stushar@ece.gatech.edu description='MeshDirCorners_XY' 4511663Stushar@ece.gatech.edu 4611663Stushar@ece.gatech.edu def __init__(self, controllers): 4711663Stushar@ece.gatech.edu self.nodes = controllers 4811663Stushar@ece.gatech.edu 4911663Stushar@ece.gatech.edu def makeTopology(self, options, network, IntLink, ExtLink, Router): 5011663Stushar@ece.gatech.edu nodes = self.nodes 5111663Stushar@ece.gatech.edu 5211663Stushar@ece.gatech.edu num_routers = options.num_cpus 5311663Stushar@ece.gatech.edu num_rows = options.mesh_rows 5411663Stushar@ece.gatech.edu 5511666Stushar@ece.gatech.edu # default values for link latency and router latency. 5611666Stushar@ece.gatech.edu # Can be over-ridden on a per link/router basis 5711666Stushar@ece.gatech.edu link_latency = options.link_latency # used by simple and garnet 5811666Stushar@ece.gatech.edu router_latency = options.router_latency # only used by garnet 5911666Stushar@ece.gatech.edu 6011666Stushar@ece.gatech.edu 6111663Stushar@ece.gatech.edu # First determine which nodes are cache cntrls vs. dirs vs. dma 6211663Stushar@ece.gatech.edu cache_nodes = [] 6311663Stushar@ece.gatech.edu dir_nodes = [] 6411663Stushar@ece.gatech.edu dma_nodes = [] 6511663Stushar@ece.gatech.edu for node in nodes: 6611663Stushar@ece.gatech.edu if node.type == 'L1Cache_Controller' or \ 6711663Stushar@ece.gatech.edu node.type == 'L2Cache_Controller': 6811663Stushar@ece.gatech.edu cache_nodes.append(node) 6911663Stushar@ece.gatech.edu elif node.type == 'Directory_Controller': 7011663Stushar@ece.gatech.edu dir_nodes.append(node) 7111663Stushar@ece.gatech.edu elif node.type == 'DMA_Controller': 7211663Stushar@ece.gatech.edu dma_nodes.append(node) 7311663Stushar@ece.gatech.edu 7411663Stushar@ece.gatech.edu # Obviously the number or rows must be <= the number of routers 7511663Stushar@ece.gatech.edu # and evenly divisible. Also the number of caches must be a 7611663Stushar@ece.gatech.edu # multiple of the number of routers and the number of directories 7711663Stushar@ece.gatech.edu # must be four. 7811666Stushar@ece.gatech.edu assert(num_rows > 0 and num_rows <= num_routers) 7911663Stushar@ece.gatech.edu num_columns = int(num_routers / num_rows) 8011663Stushar@ece.gatech.edu assert(num_columns * num_rows == num_routers) 8111663Stushar@ece.gatech.edu caches_per_router, remainder = divmod(len(cache_nodes), num_routers) 8211663Stushar@ece.gatech.edu assert(remainder == 0) 8311663Stushar@ece.gatech.edu assert(len(dir_nodes) == 4) 8411663Stushar@ece.gatech.edu 8511663Stushar@ece.gatech.edu # Create the routers in the mesh 8611666Stushar@ece.gatech.edu routers = [Router(router_id=i, latency = router_latency) \ 8711666Stushar@ece.gatech.edu for i in range(num_routers)] 8811663Stushar@ece.gatech.edu network.routers = routers 8911663Stushar@ece.gatech.edu 9011663Stushar@ece.gatech.edu # link counter to set unique link ids 9111663Stushar@ece.gatech.edu link_count = 0 9211663Stushar@ece.gatech.edu 9311663Stushar@ece.gatech.edu # Connect each cache controller to the appropriate router 9411663Stushar@ece.gatech.edu ext_links = [] 9511663Stushar@ece.gatech.edu for (i, n) in enumerate(cache_nodes): 9611663Stushar@ece.gatech.edu cntrl_level, router_id = divmod(i, num_routers) 9711663Stushar@ece.gatech.edu assert(cntrl_level < caches_per_router) 9811663Stushar@ece.gatech.edu ext_links.append(ExtLink(link_id=link_count, ext_node=n, 9911666Stushar@ece.gatech.edu int_node=routers[router_id], 10011666Stushar@ece.gatech.edu latency = link_latency)) 10111663Stushar@ece.gatech.edu link_count += 1 10211663Stushar@ece.gatech.edu 10313885Sdavid.hashe@amd.com # NUMA Node for each quadrant 10413885Sdavid.hashe@amd.com # With odd columns or rows, the nodes will be unequal 10513885Sdavid.hashe@amd.com numa_nodes = [ [], [], [], []] 10613885Sdavid.hashe@amd.com for i in xrange(num_routers): 10713885Sdavid.hashe@amd.com if i % num_columns < num_columns / 2 and \ 10813885Sdavid.hashe@amd.com i < num_routers / 2: 10913885Sdavid.hashe@amd.com numa_nodes[0].append(i) 11013885Sdavid.hashe@amd.com elif i % num_columns >= num_columns / 2 and \ 11113885Sdavid.hashe@amd.com i < num_routers / 2: 11213885Sdavid.hashe@amd.com numa_nodes[1].append(i) 11313885Sdavid.hashe@amd.com elif i % num_columns < num_columns / 2 and \ 11413885Sdavid.hashe@amd.com i >= num_routers / 2: 11513885Sdavid.hashe@amd.com numa_nodes[2].append(i) 11613885Sdavid.hashe@amd.com else: 11713885Sdavid.hashe@amd.com numa_nodes[3].append(i) 11813885Sdavid.hashe@amd.com 11913885Sdavid.hashe@amd.com num_numa_nodes = 0 12013885Sdavid.hashe@amd.com for n in numa_nodes: 12113885Sdavid.hashe@amd.com if n: 12213885Sdavid.hashe@amd.com num_numa_nodes += 1 12313885Sdavid.hashe@amd.com 12411663Stushar@ece.gatech.edu # Connect the dir nodes to the corners. 12511663Stushar@ece.gatech.edu ext_links.append(ExtLink(link_id=link_count, ext_node=dir_nodes[0], 12611666Stushar@ece.gatech.edu int_node=routers[0], 12711666Stushar@ece.gatech.edu latency = link_latency)) 12811663Stushar@ece.gatech.edu link_count += 1 12911663Stushar@ece.gatech.edu ext_links.append(ExtLink(link_id=link_count, ext_node=dir_nodes[1], 13011666Stushar@ece.gatech.edu int_node=routers[num_columns - 1], 13111666Stushar@ece.gatech.edu latency = link_latency)) 13211663Stushar@ece.gatech.edu link_count += 1 13311663Stushar@ece.gatech.edu ext_links.append(ExtLink(link_id=link_count, ext_node=dir_nodes[2], 13411666Stushar@ece.gatech.edu int_node=routers[num_routers - num_columns], 13511666Stushar@ece.gatech.edu latency = link_latency)) 13611663Stushar@ece.gatech.edu link_count += 1 13711663Stushar@ece.gatech.edu ext_links.append(ExtLink(link_id=link_count, ext_node=dir_nodes[3], 13811666Stushar@ece.gatech.edu int_node=routers[num_routers - 1], 13911666Stushar@ece.gatech.edu latency = link_latency)) 14011663Stushar@ece.gatech.edu link_count += 1 14111663Stushar@ece.gatech.edu 14211663Stushar@ece.gatech.edu # Connect the dma nodes to router 0. These should only be DMA nodes. 14311663Stushar@ece.gatech.edu for (i, node) in enumerate(dma_nodes): 14411663Stushar@ece.gatech.edu assert(node.type == 'DMA_Controller') 14511663Stushar@ece.gatech.edu ext_links.append(ExtLink(link_id=link_count, ext_node=node, 14611666Stushar@ece.gatech.edu int_node=routers[0], 14711666Stushar@ece.gatech.edu latency = link_latency)) 14811663Stushar@ece.gatech.edu 14911663Stushar@ece.gatech.edu network.ext_links = ext_links 15011663Stushar@ece.gatech.edu 15111663Stushar@ece.gatech.edu # Create the mesh links. 15211663Stushar@ece.gatech.edu int_links = [] 15311663Stushar@ece.gatech.edu 15411663Stushar@ece.gatech.edu # East output to West input links (weight = 1) 15513731Sandreas.sandberg@arm.com for row in range(num_rows): 15613731Sandreas.sandberg@arm.com for col in range(num_columns): 15711663Stushar@ece.gatech.edu if (col + 1 < num_columns): 15811663Stushar@ece.gatech.edu east_out = col + (row * num_columns) 15911663Stushar@ece.gatech.edu west_in = (col + 1) + (row * num_columns) 16011663Stushar@ece.gatech.edu int_links.append(IntLink(link_id=link_count, 16111663Stushar@ece.gatech.edu src_node=routers[east_out], 16211663Stushar@ece.gatech.edu dst_node=routers[west_in], 16311666Stushar@ece.gatech.edu src_outport="East", 16411666Stushar@ece.gatech.edu dst_inport="West", 16511666Stushar@ece.gatech.edu latency = link_latency, 16611663Stushar@ece.gatech.edu weight=1)) 16711663Stushar@ece.gatech.edu link_count += 1 16811663Stushar@ece.gatech.edu 16911663Stushar@ece.gatech.edu # West output to East input links (weight = 1) 17013731Sandreas.sandberg@arm.com for row in range(num_rows): 17113731Sandreas.sandberg@arm.com for col in range(num_columns): 17211663Stushar@ece.gatech.edu if (col + 1 < num_columns): 17311663Stushar@ece.gatech.edu east_in = col + (row * num_columns) 17411663Stushar@ece.gatech.edu west_out = (col + 1) + (row * num_columns) 17511663Stushar@ece.gatech.edu int_links.append(IntLink(link_id=link_count, 17611663Stushar@ece.gatech.edu src_node=routers[west_out], 17711663Stushar@ece.gatech.edu dst_node=routers[east_in], 17811666Stushar@ece.gatech.edu src_outport="West", 17911666Stushar@ece.gatech.edu dst_inport="East", 18011666Stushar@ece.gatech.edu latency = link_latency, 18111663Stushar@ece.gatech.edu weight=1)) 18211663Stushar@ece.gatech.edu link_count += 1 18311663Stushar@ece.gatech.edu 18411663Stushar@ece.gatech.edu # North output to South input links (weight = 2) 18513731Sandreas.sandberg@arm.com for col in range(num_columns): 18613731Sandreas.sandberg@arm.com for row in range(num_rows): 18711663Stushar@ece.gatech.edu if (row + 1 < num_rows): 18811663Stushar@ece.gatech.edu north_out = col + (row * num_columns) 18911663Stushar@ece.gatech.edu south_in = col + ((row + 1) * num_columns) 19011663Stushar@ece.gatech.edu int_links.append(IntLink(link_id=link_count, 19111663Stushar@ece.gatech.edu src_node=routers[north_out], 19211663Stushar@ece.gatech.edu dst_node=routers[south_in], 19311666Stushar@ece.gatech.edu src_outport="North", 19411666Stushar@ece.gatech.edu dst_inport="South", 19511666Stushar@ece.gatech.edu latency = link_latency, 19611663Stushar@ece.gatech.edu weight=2)) 19711663Stushar@ece.gatech.edu link_count += 1 19811663Stushar@ece.gatech.edu 19911663Stushar@ece.gatech.edu # South output to North input links (weight = 2) 20013731Sandreas.sandberg@arm.com for col in range(num_columns): 20113731Sandreas.sandberg@arm.com for row in range(num_rows): 20211663Stushar@ece.gatech.edu if (row + 1 < num_rows): 20311663Stushar@ece.gatech.edu north_in = col + (row * num_columns) 20411663Stushar@ece.gatech.edu south_out = col + ((row + 1) * num_columns) 20511663Stushar@ece.gatech.edu int_links.append(IntLink(link_id=link_count, 20611663Stushar@ece.gatech.edu src_node=routers[south_out], 20711663Stushar@ece.gatech.edu dst_node=routers[north_in], 20811666Stushar@ece.gatech.edu src_outport="South", 20911666Stushar@ece.gatech.edu dst_inport="North", 21011666Stushar@ece.gatech.edu latency = link_latency, 21111663Stushar@ece.gatech.edu weight=2)) 21211663Stushar@ece.gatech.edu link_count += 1 21311663Stushar@ece.gatech.edu 21411663Stushar@ece.gatech.edu 21511663Stushar@ece.gatech.edu network.int_links = int_links 21613885Sdavid.hashe@amd.com 21713885Sdavid.hashe@amd.com # Register nodes with filesystem 21813885Sdavid.hashe@amd.com def registerTopology(self, options): 21913885Sdavid.hashe@amd.com i = 0 22013885Sdavid.hashe@amd.com for n in numa_nodes: 22113885Sdavid.hashe@amd.com if n: 22213885Sdavid.hashe@amd.com FileSystemConfig.register_node(n, 22313885Sdavid.hashe@amd.com MemorySize(options.mem_size) / num_numa_nodes, i) 22413885Sdavid.hashe@amd.com i += 1 22513885Sdavid.hashe@amd.com 226