1# Copyright (c) 2010 Advanced Micro Devices, Inc.
2#               2016 Georgia Institute of Technology
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29#          Tushar Krishna
30
31from __future__ import print_function
32from __future__ import absolute_import
33
34from m5.params import *
35from m5.objects import *
36
37from common import FileSystemConfig
38
39from .BaseTopology import SimpleTopology
40
41# Creates a generic Mesh assuming an equal number of cache
42# and directory controllers.
43# XY routing is enforced (using link weights)
44# to guarantee deadlock freedom.
45
46class Mesh_XY(SimpleTopology):
47    description='Mesh_XY'
48
49    def __init__(self, controllers):
50        self.nodes = controllers
51
52    # Makes a generic mesh
53    # assuming an equal number of cache and directory cntrls
54
55    def makeTopology(self, options, network, IntLink, ExtLink, Router):
56        nodes = self.nodes
57
58        num_routers = options.num_cpus
59        num_rows = options.mesh_rows
60
61        # default values for link latency and router latency.
62        # Can be over-ridden on a per link/router basis
63        link_latency = options.link_latency # used by simple and garnet
64        router_latency = options.router_latency # only used by garnet
65
66
67        # There must be an evenly divisible number of cntrls to routers
68        # Also, obviously the number or rows must be <= the number of routers
69        cntrls_per_router, remainder = divmod(len(nodes), num_routers)
70        assert(num_rows > 0 and num_rows <= num_routers)
71        num_columns = int(num_routers / num_rows)
72        assert(num_columns * num_rows == num_routers)
73
74        # Create the routers in the mesh
75        routers = [Router(router_id=i, latency = router_latency) \
76            for i in range(num_routers)]
77        network.routers = routers
78
79        # link counter to set unique link ids
80        link_count = 0
81
82        # Add all but the remainder nodes to the list of nodes to be uniformly
83        # distributed across the network.
84        network_nodes = []
85        remainder_nodes = []
86        for node_index in range(len(nodes)):
87            if node_index < (len(nodes) - remainder):
88                network_nodes.append(nodes[node_index])
89            else:
90                remainder_nodes.append(nodes[node_index])
91
92        # Connect each node to the appropriate router
93        ext_links = []
94        for (i, n) in enumerate(network_nodes):
95            cntrl_level, router_id = divmod(i, num_routers)
96            assert(cntrl_level < cntrls_per_router)
97            ext_links.append(ExtLink(link_id=link_count, ext_node=n,
98                                    int_node=routers[router_id],
99                                    latency = link_latency))
100            link_count += 1
101
102        # Connect the remainding nodes to router 0.  These should only be
103        # DMA nodes.
104        for (i, node) in enumerate(remainder_nodes):
105            assert(node.type == 'DMA_Controller')
106            assert(i < remainder)
107            ext_links.append(ExtLink(link_id=link_count, ext_node=node,
108                                    int_node=routers[0],
109                                    latency = link_latency))
110            link_count += 1
111
112        network.ext_links = ext_links
113
114        # Create the mesh links.
115        int_links = []
116
117        # East output to West input links (weight = 1)
118        for row in range(num_rows):
119            for col in range(num_columns):
120                if (col + 1 < num_columns):
121                    east_out = col + (row * num_columns)
122                    west_in = (col + 1) + (row * num_columns)
123                    int_links.append(IntLink(link_id=link_count,
124                                             src_node=routers[east_out],
125                                             dst_node=routers[west_in],
126                                             src_outport="East",
127                                             dst_inport="West",
128                                             latency = link_latency,
129                                             weight=1))
130                    link_count += 1
131
132        # West output to East input links (weight = 1)
133        for row in range(num_rows):
134            for col in range(num_columns):
135                if (col + 1 < num_columns):
136                    east_in = col + (row * num_columns)
137                    west_out = (col + 1) + (row * num_columns)
138                    int_links.append(IntLink(link_id=link_count,
139                                             src_node=routers[west_out],
140                                             dst_node=routers[east_in],
141                                             src_outport="West",
142                                             dst_inport="East",
143                                             latency = link_latency,
144                                             weight=1))
145                    link_count += 1
146
147        # North output to South input links (weight = 2)
148        for col in range(num_columns):
149            for row in range(num_rows):
150                if (row + 1 < num_rows):
151                    north_out = col + (row * num_columns)
152                    south_in = col + ((row + 1) * num_columns)
153                    int_links.append(IntLink(link_id=link_count,
154                                             src_node=routers[north_out],
155                                             dst_node=routers[south_in],
156                                             src_outport="North",
157                                             dst_inport="South",
158                                             latency = link_latency,
159                                             weight=2))
160                    link_count += 1
161
162        # South output to North input links (weight = 2)
163        for col in range(num_columns):
164            for row in range(num_rows):
165                if (row + 1 < num_rows):
166                    north_in = col + (row * num_columns)
167                    south_out = col + ((row + 1) * num_columns)
168                    int_links.append(IntLink(link_id=link_count,
169                                             src_node=routers[south_out],
170                                             dst_node=routers[north_in],
171                                             src_outport="South",
172                                             dst_inport="North",
173                                             latency = link_latency,
174                                             weight=2))
175                    link_count += 1
176
177
178        network.int_links = int_links
179
180    # Register nodes with filesystem
181    def registerTopology(self, options):
182        for i in xrange(options.num_cpus):
183            FileSystemConfig.register_node([i],
184                    MemorySize(options.mem_size) / options.num_cpus, i)
185