Searched refs:OperatingMode (Results 1 - 15 of 15) sorted by relevance

/gem5/src/arch/arm/
H A Dutility.hh146 static inline OperatingMode
150 return (OperatingMode) (uint8_t) cpsr.mode;
162 return opModeToEL((OperatingMode) (uint8_t)cpsr.mode);
200 * @param mode OperatingMode to check
203 bool badMode32(ThreadContext *tc, OperatingMode mode);
210 * @param mode OperatingMode to check
213 bool badMode(ThreadContext *tc, OperatingMode mode);
239 switch ((OperatingMode) (uint8_t) cpsr.mode) {
H A Dtypes.hh592 enum OperatingMode { enum in namespace:ArmISA
670 opModeIs64(OperatingMode mode)
676 opModeIsH(OperatingMode mode)
682 opModeIsT(OperatingMode mode)
689 opModeToEL(OperatingMode mode)
718 unknownMode(OperatingMode mode)
744 unknownMode32(OperatingMode mode)
H A Dfaults.hh76 OperatingMode fromMode; // Source operating mode (aarch32)
77 OperatingMode toMode; // Next operating mode (aarch32)
164 const OperatingMode nextMode;
187 const OperatingMode& nextMode_, const uint8_t& armPcOffset_,
224 virtual OperatingMode nextMode() = 0;
257 OperatingMode nextMode() override { return vals.nextMode; }
H A Dutility.cc215 return opModeIs64((OperatingMode) (uint8_t) cpsr.mode);
373 badMode32(ThreadContext *tc, OperatingMode mode)
379 badMode(ThreadContext *tc, OperatingMode mode)
703 OperatingMode mode = MODE_UNDEFINED;
771 mode = (OperatingMode) ( ((sysM2 || sysM1) << 0) |
H A Dintregs.hh464 intRegInMode(OperatingMode mode, int reg)
H A Dfaults.cc429 fromMode = (OperatingMode) (uint8_t) cpsr.mode;
850 OperatingMode mode = (OperatingMode)(uint8_t)cpsr.mode;
H A Disa.hh483 (OperatingMode) (uint8_t) cpsr.mode);
/gem5/src/arch/arm/tracers/
H A Dtarmac_base.hh97 ArmISA::OperatingMode mode;
H A Dtarmac_base.cc77 mode = (OperatingMode) (uint8_t)cpsr.mode;
H A Dtarmac_record.cc66 opModeToStr(OperatingMode opMode)
253 OperatingMode mode = (OperatingMode)(uint8_t)cpsr.mode;
H A Dtarmac_record.hh79 opModeToStr(ArmISA::OperatingMode opMode);
/gem5/src/arch/x86/
H A Dtypes.hh181 BitUnion8(OperatingMode)
184 EndBitUnion(OperatingMode)
235 OperatingMode mode;
/gem5/src/arch/arm/insts/
H A Dstatic_inst.hh234 OperatingMode newMode = (OperatingMode) (val & mask(5));
235 OperatingMode oldMode = (OperatingMode)(uint32_t)cpsr.mode;
H A Dstatic_inst.cc1025 const ExceptionLevel el = opModeToEL((OperatingMode) (uint8_t)spsr.mode);
1052 const OperatingMode mode = (OperatingMode) (uint8_t)spsr.mode;
1056 const OperatingMode cur_mode = (OperatingMode) (uint8_t)cpsr.mode;
1121 if (spsr.width && unknownMode32((OperatingMode)(uint8_t)spsr.mode)) {
/gem5/src/dev/arm/
H A Dgic_v3_cpu_interface.cc2340 bool is_64 = opModeIs64((OperatingMode)(uint8_t) cpsr.mode);
2392 return opModeIs64((OperatingMode)(uint8_t) cpsr.mode);
2400 bool is_64 = opModeIs64((OperatingMode)(uint8_t) cpsr.mode);

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