Searched refs:Malta (Results 1 - 8 of 8) sorted by relevance
| /gem5/src/dev/mips/ |
| H A D | malta.cc | 33 * Implementation of Malta platform.
43 #include "debug/Malta.hh"
46 #include "params/Malta.hh"
51 Malta::Malta(const Params *p) function in class:Malta
54 for (int i = 0; i < Malta::Max_CPUs; i++)
59 Malta::postConsoleInt()
66 Malta::clearConsoleInt()
73 Malta::postPciInt(int line)
75 panic("Malta
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| H A D | malta.hh | 34 * Declaration of top level class for the Malta chipset. This class just
42 #include "params/Malta.hh"
50 * Top level class for Malta Chipset emulation.
56 class Malta : public Platform class in inherits:Platform
59 /** Max number of CPUs in a Malta */
68 /** Pointer to the Malta CChip.
74 int intr_sum_type[Malta::Max_CPUs];
75 int ipi_pending[Malta::Max_CPUs];
79 * Constructor for the Malta Class.
85 Malta(cons
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| H A D | malta_cchip.cc | 33 * Emulation of the Malta CChip CSRs
45 #include "debug/Malta.hh"
109 assert(size <= Malta::Max_CPUs);
112 //Note: Malta does not use index, but this was added to use the
115 DPRINTF(Malta, "posting interrupt to cpu %d, interrupt %d\n",
124 assert(size <= Malta::Max_CPUs);
127 //Note: Malta does not use index, but this was added to use the
130 DPRINTF(Malta, "clearing interrupt to cpu %d, interrupt %d\n",
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| H A D | malta_io.hh | 34 * Malta I/O Space mapping including RTC/timer interrupts
49 * Malta I/O device is a catch all for all the south bridge stuff we care
59 Malta *malta;
88 /** A pointer to the Malta device which be belong to */
89 Malta *malta;
118 * Initialize all the data for devices supported by Malta I/O.
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| H A D | Malta.py | 40 malta = Param.Malta(Parent.any, "Malta")
49 malta = Param.Malta(Parent.any, "Malta")
52 class Malta(Platform): class in inherits:Platform
53 type = 'Malta'
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| H A D | malta_cchip.hh | 33 * Emulation of the Malta CChip CSRs
44 * Malta CChip CSR Emulation. This device includes all the interrupt
55 Malta *malta;
61 //uint64_t dim[Malta::Max_CPUs];
67 //uint64_t dir[Malta::Max_CPUs];
91 * Initialize the Malta CChip by setting all of the
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| H A D | malta_io.cc | 34 * Malta I/O including PIC, PIT, RTC, DMA
47 #include "debug/Malta.hh"
102 DPRINTF(Malta, "posting pic interrupt to cchip\n");
109 DPRINTF(Malta, "clear pic interrupt to cchip\n");
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| /gem5/configs/common/ |
| H A D | FSConfig.py | 400 class BaseMalta(Malta):
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