15222Sksewell@umich.edu/* 25222Sksewell@umich.edu * Copyright (c) 2004-2005 The Regents of The University of Michigan 35222Sksewell@umich.edu * All rights reserved. 45222Sksewell@umich.edu * 55222Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 65222Sksewell@umich.edu * modification, are permitted provided that the following conditions are 75222Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 85222Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 95222Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 105222Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 115222Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 125222Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 135222Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 145222Sksewell@umich.edu * this software without specific prior written permission. 155222Sksewell@umich.edu * 165222Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175222Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185222Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195222Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205222Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215222Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225222Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235222Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245222Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255222Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265222Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275222Sksewell@umich.edu * 285222Sksewell@umich.edu * Authors: Ali Saidi 295222Sksewell@umich.edu * Andrew Schultz 305222Sksewell@umich.edu * Miguel Serrano 315222Sksewell@umich.edu */ 325222Sksewell@umich.edu 335222Sksewell@umich.edu/** @file 345222Sksewell@umich.edu * Malta I/O Space mapping including RTC/timer interrupts 355222Sksewell@umich.edu */ 365222Sksewell@umich.edu 375222Sksewell@umich.edu#ifndef __DEV_MALTA_IO_HH__ 385222Sksewell@umich.edu#define __DEV_MALTA_IO_HH__ 395222Sksewell@umich.edu 405222Sksewell@umich.edu#include "dev/mips/malta.hh" 419338SAndreas.Sandberg@arm.com#include "dev/mips/malta_cchip.hh" 426379Sgblack@eecs.umich.edu#include "dev/intel_8254_timer.hh" 436379Sgblack@eecs.umich.edu#include "dev/io_device.hh" 446379Sgblack@eecs.umich.edu#include "dev/mc146818.hh" 456379Sgblack@eecs.umich.edu#include "params/MaltaIO.hh" 465222Sksewell@umich.edu#include "sim/eventq.hh" 475222Sksewell@umich.edu 485222Sksewell@umich.edu/** 495222Sksewell@umich.edu * Malta I/O device is a catch all for all the south bridge stuff we care 505222Sksewell@umich.edu * to implement. 515222Sksewell@umich.edu */ 525222Sksewell@umich.educlass MaltaIO : public BasicPioDevice 535222Sksewell@umich.edu{ 545222Sksewell@umich.edu protected: 556379Sgblack@eecs.umich.edu 566379Sgblack@eecs.umich.edu class RTC : public MC146818 575222Sksewell@umich.edu { 586379Sgblack@eecs.umich.edu public: 596379Sgblack@eecs.umich.edu Malta *malta; 606379Sgblack@eecs.umich.edu RTC(const std::string &name, const MaltaIOParams *p); 616379Sgblack@eecs.umich.edu 626379Sgblack@eecs.umich.edu protected: 636379Sgblack@eecs.umich.edu void handleEvent() 645222Sksewell@umich.edu { 656379Sgblack@eecs.umich.edu //Actually interrupt the processor here 666379Sgblack@eecs.umich.edu malta->cchip->postRTC(); 676379Sgblack@eecs.umich.edu } 685222Sksewell@umich.edu }; 695222Sksewell@umich.edu 705222Sksewell@umich.edu /** Mask of the PIC1 */ 715222Sksewell@umich.edu uint8_t mask1; 725222Sksewell@umich.edu 735222Sksewell@umich.edu /** Mask of the PIC2 */ 745222Sksewell@umich.edu uint8_t mask2; 755222Sksewell@umich.edu 765222Sksewell@umich.edu /** Mode of PIC1. Not used for anything */ 775222Sksewell@umich.edu uint8_t mode1; 785222Sksewell@umich.edu 795222Sksewell@umich.edu /** Mode of PIC2. Not used for anything */ 805222Sksewell@umich.edu uint8_t mode2; 815222Sksewell@umich.edu 825222Sksewell@umich.edu /** Raw PIC interrupt register before masking */ 835222Sksewell@umich.edu uint8_t picr; //Raw PIC interrput register 845222Sksewell@umich.edu 855222Sksewell@umich.edu /** Is the pic interrupting right now or not. */ 865222Sksewell@umich.edu bool picInterrupting; 875222Sksewell@umich.edu 885222Sksewell@umich.edu /** A pointer to the Malta device which be belong to */ 895222Sksewell@umich.edu Malta *malta; 905222Sksewell@umich.edu 915222Sksewell@umich.edu /** Intel 8253 Periodic Interval Timer */ 926379Sgblack@eecs.umich.edu Intel8254Timer pitimer; 935222Sksewell@umich.edu 945222Sksewell@umich.edu RTC rtc; 955222Sksewell@umich.edu 965222Sksewell@umich.edu /** The interval is set via two writes to the PIT. 975222Sksewell@umich.edu * This variable contains a flag as to how many writes have happened, and 985222Sksewell@umich.edu * the time so far. 995222Sksewell@umich.edu */ 1005222Sksewell@umich.edu uint16_t timerData; 1015222Sksewell@umich.edu 1025222Sksewell@umich.edu public: 1035222Sksewell@umich.edu /** 1045222Sksewell@umich.edu * Return the freqency of the RTC 1055222Sksewell@umich.edu * @return interrupt rate of the RTC 1065222Sksewell@umich.edu */ 1075222Sksewell@umich.edu Tick frequency() const; 1085222Sksewell@umich.edu 1095222Sksewell@umich.edu typedef MaltaIOParams Params; 1105222Sksewell@umich.edu 1115222Sksewell@umich.edu const Params * 1125222Sksewell@umich.edu params() const 1135222Sksewell@umich.edu { 1145222Sksewell@umich.edu return dynamic_cast<const Params *>(_params); 1155222Sksewell@umich.edu } 1165222Sksewell@umich.edu 1175222Sksewell@umich.edu /** 1185222Sksewell@umich.edu * Initialize all the data for devices supported by Malta I/O. 1195222Sksewell@umich.edu * @param p pointer to Params struct 1205222Sksewell@umich.edu */ 1216379Sgblack@eecs.umich.edu MaltaIO(const Params *p); 1225222Sksewell@umich.edu 12311347Sandreas.hansson@arm.com Tick read(PacketPtr pkt) override; 12411347Sandreas.hansson@arm.com Tick write(PacketPtr pkt) override; 1255222Sksewell@umich.edu 1265222Sksewell@umich.edu 1276379Sgblack@eecs.umich.edu /** Post an Interrupt to the CPU */ 1286379Sgblack@eecs.umich.edu void postIntr(uint8_t interrupt); 1296379Sgblack@eecs.umich.edu 1306379Sgblack@eecs.umich.edu /** Clear an Interrupt to the CPU */ 1316379Sgblack@eecs.umich.edu void clearIntr(uint8_t interrupt); 1325222Sksewell@umich.edu 13311168Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 13411168Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 1355222Sksewell@umich.edu 13610631Scdirik@micron.com /** 13710631Scdirik@micron.com * Start running. 13810631Scdirik@micron.com */ 13911347Sandreas.hansson@arm.com void startup() override; 14010631Scdirik@micron.com 1415222Sksewell@umich.edu}; 1425222Sksewell@umich.edu 1435222Sksewell@umich.edu#endif // __DEV_MALTA_IO_HH__ 144