Searched refs:EL1 (Results 1 - 16 of 16) sorted by relevance

/gem5/src/arch/arm/insts/
H A Dmisc64.cc93 if (el <= EL1 && checkEL1Trap(tc, misc_reg, el)) {
133 (el == EL1 && !(cpacr.fpen & 0x1)))
165 trap_to_hyp = cptr.tcpac && el == EL1;
181 el == EL1;
196 trap_to_hyp = hcr.ttlb && el == EL1;
203 trap_to_hyp = hcr.tpu && el <= EL1;
210 trap_to_hyp = hcr.tpc && el <= EL1;
216 trap_to_hyp = hcr.tsw && el == EL1;
220 trap_to_hyp = hcr.tacr && el == EL1;
256 trap_to_hyp = hcr.tid3 && el == EL1;
[all...]
H A Dstatic_inst.cc637 !ELIs32(tc, EL1)) {
651 case EL1:
691 (el == EL1 && !(cpacr.fpen & 0x1)))
692 return advSIMDFPAccessTrap64(EL1);
708 if (cur_el == EL0 && ELIs64(tc, EL1))
785 case EL1:
823 case EL1:
856 case EL1:
882 fault = checkForWFxTrap32(tc, EL1, isWfe);
887 ((curr_el == EL0) || (curr_el == EL1))) {
[all...]
/gem5/src/arch/arm/
H A Disa.cc283 case EL1:
722 0x0000000000000020 | // EL1
1114 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1124 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1134 ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1144 DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1158 TLBIMVA tlbiOp(EL1,
1173 TLBIMVA tlbiOp(EL1,
1187 TLBIASID tlbiOp(EL1,
1200 TLBIASID tlbiOp(EL1,
[all...]
H A Dutility.cc240 case EL1:
347 || (aarch32_at_el1 && (el == EL0 || el == EL1) );
362 case EL1:
390 case EL1:
422 case EL1:
826 case EL1:
H A Dinterrupts.cc104 if (!is_secure && (el == EL0 || el == EL1))
H A Dsystem.hh236 return EL1;
H A Dsystem.cc230 return FullSystem? getArmSystem(tc)->highestEL() : EL1;
238 case EL1:
H A Dtypes.hh587 EL1, enumerator in enum:ArmISA::ExceptionLevel
702 return EL1;
H A Dtlb.cc128 aarch64 ? aarch64EL : EL1);
266 stage2Tlb->flushAllSecurity(secure_lookup, EL1, true);
297 stage2Tlb->flushAllNs(EL1, true);
915 case EL1:
936 // executable at EL1
1313 ELIs64(tc, aarch64EL == EL0 ? EL1 : aarch64EL);
1319 case EL1:
1432 return EL1;
1466 ExceptionLevel target_el = aarch64 ? aarch64EL : EL1;
H A Dpagetable.hh227 return (el == EL0) || (el == EL1);
H A Dfaults.cc340 case EL1:
354 case EL1:
370 case EL1:
454 if (toEL == EL1) {
624 case EL1:
966 lower_32 = ELIs32(tc, EL1);
1592 return have_el2 && !inSecureState(tc) && fromEL <= EL1 &&
H A Dtable_walker.cc235 // even AArch32 EL0 will use AArch64 translation if EL1 is in AArch64.
237 currState->el = EL1;
243 ELIs64(_tc, currState->el == EL0 ? EL1 : currState->el);
273 case EL1:
763 case EL1:
1398 case EL1:
2071 te.el = EL1;
H A Dpmu.cc509 case EL1:
H A Disa.hh491 case EL1:
H A Dmiscregs.cc1142 case EL1:
1186 case EL1:
2860 // Set Privileged Access Never on taking an exception to EL1 (Arm 8.1+),
3606 .privRead(FullSystem && system->highestEL() == EL1)
/gem5/src/dev/arm/
H A Dgic_v3_cpu_interface.cc124 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
147 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
167 // Interrupt Group 0 Enable register EL1
170 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
184 // Interrupt Group 1 Enable register EL1
187 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
219 if ((currEL() == EL1) && !inSecureState() &&
255 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
285 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
315 if ((currEL() == EL1)
[all...]

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