Searched refs:EL0 (Results 1 - 17 of 17) sorted by relevance

/gem5/src/arch/arm/
H A Dutility.cc233 case EL0:
235 // checking access permissions. This means that EL0 entry must
238 warn_once("Trying to read MPIDR at EL0\n");
306 (el == EL2 || (el == EL0 && hcr.tge == 1)));
337 // Only know if EL0 using AArch32 from PSTATE
338 if (el == EL0 && !aarch32_at_el1) {
339 // EL0 controlled by PSTATE
342 known = (currEL(tc) == EL0);
347 || (aarch32_at_el1 && (el == EL0 || el == EL1) );
364 case EL0
[all...]
H A Dpagetable.hh135 // Exception level on insert, AARCH64 EL0&1, AARCH32 -> el=1
157 ns(true), nstid(true), el(EL0), nonCacheable(uncacheable),
172 ns(true), nstid(true), el(EL0), nonCacheable(false),
227 return (el == EL0) || (el == EL1);
H A Dinterrupts.cc104 if (!is_secure && (el == EL0 || el == EL1))
H A Dtlb.hh76 * @param is_priv Access from a privileged mode (i.e., not EL0)
91 * @param is_priv Access from a privileged mode (i.e., not EL0)
268 flushAllSecurity(false, EL0, true);
269 flushAllSecurity(true, EL0, true);
H A Dtypes.hh586 EL0 = 0, enumerator in enum:ArmISA::ExceptionLevel
695 return EL0;
H A Dsystem.cc237 case EL0:
H A Dtlb.cc81 aarch64(false), aarch64EL(EL0), isPriv(false), isSecure(false),
792 // * It is executed from EL0
793 if (req->isCacheClean() && aarch64EL != EL0 && !isStage2) {
883 case EL0:
935 // regions that are writeable at EL0 should not be
1313 ELIs64(tc, aarch64EL == EL0 ? EL1 : aarch64EL);
1318 case EL0:
1343 isPriv = aarch64EL != EL0;
1428 return EL0;
H A Dfaults.hh203 fromEL(EL0), toEL(EL0), fromMode(MODE_UNDEFINED),
H A Disa.hh484 if (!cpsr.sp && el != EL0)
493 case EL0:
H A Dtable_walker.cc131 tc(nullptr), aarch64(false), el(EL0), physAddrRange(0), req(nullptr),
235 // even AArch32 EL0 will use AArch64 translation if EL1 is in AArch64.
243 ELIs64(_tc, currState->el == EL0 ? EL1 : currState->el);
272 case EL0:
762 case EL0:
1397 case EL0:
H A Disa.cc721 return 0x0000000000000002 | // AArch{64,32} supported at EL0
1109 case MISCREG_TLBIALL: // TLBI all entries, EL0&1,
2137 if (el == EL1 || (el == EL0 && !ELIsInHost(tc, el))) {
2141 if (el == EL2 || (el == EL0 && ELIsInHost(tc, el))) {
2144 (el == EL0 || el == EL1)) {
H A Dpmu.cc506 case EL0:
H A Dmiscregs.cc1139 case EL0:
1164 if (el == EL0 && !sctlr.uma)
1169 // allowed at EL0
1171 if (el == EL0 && !sctlr.dze)
1176 if (el == EL0 && !sctlr.uci)
1183 case EL0:
H A Dfaults.cc1017 toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (currEL(tc) == EL0);
1539 toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (currEL(tc) == EL0);
/gem5/src/arch/arm/insts/
H A Dstatic_inst.cc690 if ((el == EL0 && cpacr.fpen != 0x3) ||
708 if (cur_el == EL0 && ELIs64(tc, EL1))
725 if ((cur_el == EL0 && cpacr_cp10 != 0x3) ||
726 (cur_el != EL0 && !(cpacr_cp10 & 0x1)))
881 if (curr_el == EL0) {
887 ((curr_el == EL0) || (curr_el == EL1))) {
914 // instruction executed at EL0, and with an AArch64 EL1.
956 case EL0:
1012 if ((el == EL0 && cpacr.zen != 0x3) ||
1077 assert(known || (target_el == EL0
[all...]
H A Dmisc64.cc132 if ((el == EL0 && cpacr.fpen != 0x3) ||
/gem5/src/dev/arm/
H A Dgic_v3_cpu_interface.cc2365 case EL0:

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