| /gem5/src/arch/arm/ |
| H A D | tlb.hh | 89 * @param va Virtual address that initiated the walk
96 virtual Fault walkCheck(Addr pa, Addr size, Addr va, bool is_secure,
272 /** Remove any entries that match both a va and asn
287 /** Remove all entries that match the va regardless of asn
304 Fault walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz,
449 /** Remove any entries that match both a va and asn
461 Fault testWalk(Addr pa, Addr size, Addr va, bool is_secure, Mode mode,
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| H A D | tlb.cc | 118 TLB::translateFunctional(ThreadContext *tc, Addr va, Addr &pa) argument
124 return stage2Tlb->translateFunctional(tc, va, pa);
127 TlbEntry *e = lookup(va, asid, vmid, isHyp, isSecure, true, false,
131 pa = e->pAddr(va);
152 TLB::lookup(Addr va, uint16_t asn, uint8_t vmid, bool hyp, bool secure, argument
161 if ((!ignore_asn && table[x].match(va, asn, vmid, hyp, secure, false,
163 (ignore_asn && table[x].match(va, vmid, hyp, secure, target_el))) {
183 va, asn, retval ? "hit" : "miss", vmid, hyp, secure,
185 retval ? retval->pAddr(va) : 0, retval ? retval->ap : 0,
1615 TLB::testWalk(Addr pa, Addr size, Addr va, boo argument
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| H A D | faults.hh | 238 virtual bool getFaultVAddr(Addr &va) const { return false; }
441 bool getFaultVAddr(Addr &va) const override;
636 * If true it is storing the faulting address in the va argument
639 * @param va function will modify this passed-by-reference parameter
641 * @return true if va contains a valid value, false otherwise
643 bool getFaultVAddr(Fault fault, Addr &va);
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| H A D | faults.cc | 1236 AbortFault<T>::getFaultVAddr(Addr &va) const
1238 va = (stage2 ? OVAddr : faultAddr);
1426 hcr.va = 0;
1645 getFaultVAddr(Fault fault, Addr &va) argument
1650 return arm_fault->getFaultVAddr(va);
1654 va = pgt_fault->getFaultVAddr();
1660 va = align_fault->getFaultVAddr();
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| H A D | miscregs_types.hh | 263 Bitfield<8> va; member in namespace:ArmISA
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| /gem5/src/arch/x86/ |
| H A D | tlb.cc | 121 TLB::lookup(Addr va, bool update_lru) argument
123 TlbEntry *entry = trie.lookup(va);
162 TLB::demapPage(Addr va, uint64_t asn) argument
164 TlbEntry *entry = trie.lookup(va);
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| /gem5/src/gpu-compute/ |
| H A D | gpu_tlb.cc | 183 GpuTLB::lookupIt(Addr va, bool update_lru) argument
185 int set = (va >> TheISA::PageShift) & setMask;
195 if ((*entry)->vaddr <= va && (*entry)->vaddr + page_size > va) {
197 "with size %#x.\n", va, (*entry)->vaddr, page_size);
213 GpuTLB::lookup(Addr va, bool update_lru) argument
215 int set = (va >> TheISA::PageShift) & setMask;
217 auto entry = lookupIt(va, update_lru);
264 GpuTLB::demapPage(Addr va, uint64_t asn) argument
267 int set = (va >> TheIS
[all...] |
| /gem5/src/dev/arm/ |
| H A D | smmu_v3_transl.cc | 421 e.va = request.addr & e.vaMask;
431 e.va, e.vaMask, e.pa, e.sid, e.ssid);
453 e.va = request.addr & e.vaMask;
468 "ssid=%#x\n", e.va, e.vaMask, e.pa, e.sid, e.ssid);
487 e.va = request.addr & e.vaMask;
497 e.va, e.vaMask, e.pa, e.asid, e.vmid);
674 DPRINTF(SMMUv3, "%sWalkCache hit va=%#x asid=%#x vmid=%#x "
678 DPRINTF(SMMUv3, "%sWalkCache miss va=%#x asid=%#x vmid=%#x "
688 SMMUTranslationProcess::walkCacheUpdate(Yield &yield, Addr va, argument
699 e.va
[all...] |
| H A D | smmu_v3_defs.hh | 393 uint64_t va; member in struct:SMMUEvent
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| /gem5/system/alpha/h/ |
| H A D | ev5_defs.h | 141 #define va 518 macro
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| /gem5/system/alpha/palcode/ |
| H A D | osfpal.S | 220 bic r14, 3, r16 // pass pc/va as a0
537 mfpr r16, pt0 // a0 <- va/unlock
859 bis r25, r31, r16 // a0 <- va
930 mfpr r31, va // unlock VA
978 mfpr r31, va // unlock the mbox
1296 or r10, r31, r14 // Save pc/va in case TBmiss or fault on stack
1300 or r14, r31, r16 // pass pc/va as a0
1355 or r10, r31, r14 // Save pc/va in case TBmiss on stack
1359 or r14, r31, r16 // pass pc/va as a0
1389 // R10 = va
[all...] |
| H A D | platform.S | 1449 mfpr r31, va // unlock va, mmstat
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