Searched refs:scheduled (Results 51 - 75 of 88) sorted by relevance

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/gem5/src/mem/
H A Dsimple_mem.cc150 // to avoid extra events being scheduled for (infinitely) fast
184 if (!retryResp && !dequeueEvent.scheduled())
219 // already have an event scheduled, so use re-schedule
/gem5/src/cpu/
H A Dbase.cc491 if (enterPwrGatingEvent.scheduled()){
506 assert(!enterPwrGatingEvent.scheduled());
528 if (enterPwrGatingEvent.scheduled())
577 if (profileEvent && profileEvent->scheduled())
H A Dthread_context.cc274 if (oqe->scheduled()) {
/gem5/src/dev/net/
H A Dethertap.cc200 if (!txEvent.scheduled())
222 if (!packetBuffer.empty() && !txEvent.scheduled())
H A Detherswitch.cc101 // scheduled for the old head of queue packet and schedule a new one
175 // otherwise, there is already a txEvent scheduled
189 if (!txEvent.scheduled())
279 bool event_scheduled = txEvent.scheduled();
H A Di8254xGBe.hh332 return wbEvent.scheduled() || fetchEvent.scheduled();
/gem5/src/dev/storage/
H A Dide_disk.cc683 /** @todo make this a scheduled event to simulate disk delay */
923 /** @todo change this to a scheduled event to simulate
999 /** @todo change this to a scheduled event to simulate
1081 // Check all outstanding events to see if they are scheduled
1088 if (dmaTransferEvent.scheduled()) {
1093 if (dmaReadWaitEvent.scheduled()) {
1098 if (dmaWriteWaitEvent.scheduled()) {
1103 if (dmaPrdReadEvent.scheduled()) {
1108 if (dmaReadEvent.scheduled()) {
1113 if (dmaWriteEvent.scheduled()) {
[all...]
/gem5/src/cpu/o3/
H A Dcpu.cc567 if (!tickEvent.scheduled()) {
996 if (tickEvent.scheduled())
1023 if (tickEvent.scheduled())
1112 assert(!tickEvent.scheduled());
1147 assert(!tickEvent.scheduled());
1701 if (activityRec.active() || tickEvent.scheduled()) {
1806 if (!threadExitEvent.scheduled()) {
H A Dcpu.hh147 else if (!tickEvent.scheduled())
154 if (tickEvent.scheduled())
/gem5/src/arch/sparc/
H A Disa.cc703 if (tickCompare && tickCompare->scheduled())
705 if (sTickCompare && sTickCompare->scheduled())
707 if (hSTickCompare && hSTickCompare->scheduled())
/gem5/src/arch/x86/
H A Dinterrupts.cc390 if (apicTimerEvent.scheduled()) {
738 bool apicTimerEventScheduled = apicTimerEvent.scheduled();
768 if (apicTimerEvent.scheduled()) {
/gem5/src/dev/arm/
H A Dflash_device.cc161 * The function determines when certain actions are scheduled and schedules
266 DPRINTF(FlashDevice, "scheduled at: %ld\n", cbe.time);
268 if (!planeEvent.scheduled())
302 * Invariant: All queued events are scheduled in the present
572 if (planeEvent.scheduled()) {
H A Dpl011.cc292 if (!intEvent.scheduled())
H A Dsmmu_v3_slaveifc.cc247 if (deviceNeedsRetry && !sendDeviceRetryEvent.scheduled()) {
H A Dgeneric_timer.cc127 if (_counterLimitReachedEvent.scheduled())
210 if (_counterLimitReachedEvent.scheduled())
H A Dvgic.cc367 if (!(postVIntEvent[cpu]->scheduled()))
463 if (postVIntEvent[cpu]->scheduled()) {
H A Dufs_device.cc1339 DPRINTF(UFSHostDevice, "Transfer scheduled\n");
1453 assert(!SCSIResumeEvent.scheduled());
1464 DPRINTF(UFSHostDevice, "SCSI scheduled\n");
1509 DPRINTF(UFSHostDevice, "Transfer scheduled");
1526 panic("No SCSI message scheduled lun:%d Doorbell: 0x%8x", lun_id,
1713 panic("No SCSI message scheduled lun:%d Doorbell: 0x%8x", lun_id,
1898 assert(!writeDoneEvent.back().scheduled());
1916 DPRINTF(UFSHostDevice, "Write to disk scheduled\n");
1919 assert(!additional_action->scheduled());
1922 DPRINTF(UFSHostDevice, "Write scheduled\
[all...]
/gem5/src/sim/
H A Deventq.hh61 //! event to scheduled on Queue A which is generated by an event on
102 static const FlagsType Scheduled = 0x0002; // has been scheduled
119 /// Event priorities, to provide tie-breakers for events scheduled
120 /// at the same cycle. Most events are scheduled at the default
144 /// scheduled before regular writebacks (which have default
224 /// scheduled on this queue yet)
230 Tick whenScheduled; //!< time scheduled
309 * releaseImpl()) or checking if an event is no longer scheduled
314 * Managed event scheduled and being held in the event queue.
333 if (!scheduled())
385 bool scheduled() const { return flags.isSet(Scheduled); } function in class:Event
[all...]
/gem5/src/cpu/testers/garnet_synthetic_traffic/
H A DGarnetSyntheticTraffic.cc179 if (!tickEvent.scheduled())
/gem5/src/mem/ruby/system/
H A DGPUCoalescer.cc324 if (!deadlockCheckEvent.scheduled()) {
717 if (!issueEvent.scheduled()) {
811 if (!issueEvent.scheduled()) {
865 if (!issueEvent.scheduled())
H A DSequencer.hh91 { return deadlockCheckEvent.scheduled(); }
H A DGPUCoalescer.hh169 return deadlockCheckEvent.scheduled();
/gem5/src/systemc/core/
H A Dscheduler.hh76 * readyEvent to be scheduled with slightly lowered priority, ensuring it
79 * Because delta notifications are scheduled at the standard priority, all
81 * if the readyEvent was scheduled above, there shouldn't be any higher
101 * delta notifications/timeouts which will have been scheduled during either
106 * readyEvent will have been scheduled and will be waiting and ready to run
121 * cycle's delta notification phase, an event is scheduled with a lower than
123 * delta notifications which are scheduled with normal priority will happen
126 * delta cycle. All of these events are scheduled for the current time, and so
132 * scheduled so that it happens before any of the delta notification events
333 // Run scheduled channe
[all...]
/gem5/src/cpu/simple/
H A Dtiming.hh348 * <li>A fetch event is scheduled. Normally this would never be the
358 !fetchEvent.scheduled();
/gem5/src/gpu-compute/
H A Dshader.cc156 // apply any scheduled adds
192 if (!tickEvent.scheduled()) {

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