/gem5/src/cpu/pred/ |
H A D | tage_sc_l.hh | 105 int gindex(ThreadID tid, Addr pc, int bank) const override; 109 virtual uint16_t gtag(ThreadID tid, Addr pc, int bank) const override = 0;
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H A D | multiperspective_perceptron_tage.hh | 197 MPPTAGEBranchInfo(Addr pc, int pcshift, bool cond, TAGEBase &tage, argument 200 : MPPBranchInfo(pc, pcshift, cond), 232 void uncondBranch(ThreadID tid, Addr pc, void * &bp_history) override;
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H A D | tage_base.cc | 223 // gindex computes a full hash of pc, ghist and pathHist 225 TAGEBase::gindex(ThreadID tid, Addr pc, int bank) const argument 230 const unsigned int shiftedPc = pc >> instShiftAmt; 243 TAGEBase::gtag(ThreadID tid, Addr pc, int bank) const argument 245 int tag = (pc >> instShiftAmt) ^ 288 TAGEBase::getBimodePred(Addr pc, BranchInfo* bi) const argument 297 TAGEBase::baseUpdate(Addr pc, bool taken, BranchInfo* bi) argument 311 DPRINTF(Tage, "Updating branch %lx, pred:%d, hyst:%d\n", pc, pred, hyst); 358 Addr pc = branch_pc; local 364 calculateIndicesAndTags(tid, pc, b [all...] |
/gem5/util/statetrace/arch/sparc/ |
H A D | tracechild.hh | 80 //This calculates where the pc might go after the current instruction. 83 int getTargets(uint32_t inst, uint64_t pc, uint64_t npc,
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/gem5/src/arch/hsail/insts/ |
H A D | branch.hh | 136 w->pc(getTargetPc()); 264 const uint32_t curr_pc M5_VAR_USED = w->pc(); 298 assert(w->pc() != curr_pc); 410 w->pc(getTargetPc());
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/gem5/src/arch/power/insts/ |
H A D | floating.hh | 149 Addr pc, const SymbolTable *symtab) const override;
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/gem5/src/arch/sparc/insts/ |
H A D | static_inst.hh | 94 Addr pc, const SymbolTable *symtab) const override;
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/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64mi/ |
H A D | access.S | 24 # after the pc is set to rs1, an access exception should be raised.
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/gem5/src/arch/x86/ |
H A D | utility.cc | 82 PCState pc = tc->pcState(); local 83 pc.upc(0); 84 pc.nupc(1); 85 tc->pcState(pc);
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/gem5/util/ |
H A D | decode_inst_dep_trace.py | 74 # instruction sequence number, (optional) pc, (optional) weight, type 80 # seq_num,[pc],[weight,]type,[p_addr,size,flags,]comp_delay:[rob_dep]: 162 # Write to file the pc of the instruction, default is 0 163 if packet.HasField('pc'): 164 ascii_out.write(',%s' % (packet.pc))
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H A D | encode_inst_dep_trace.py | 74 # instruction sequence number, (optional) pc, (optional) weight, type, 80 # seq_num,[pc],[weight,]type,[p_addr,size,flags,]comp_delay:[rob_dep]: 156 dep_record.pc = long(inst_info_list[1])
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/gem5/src/arch/arm/tracers/ |
H A D | tarmac_record.cc | 121 : InstEntry(tarmCtx.thread, tarmCtx.pc, tarmCtx.staticInst, predicate) 154 : RegEntry(tarmCtx.pc), 263 regName = "pc"; 345 pc
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/gem5/src/arch/riscv/ |
H A D | process.cc | 116 PCState pc = system->getThreadContext(ctx)->pcState(); local 117 pc.rv32(true); 118 system->getThreadContext(ctx)->pcState(pc);
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/gem5/src/cpu/minor/ |
H A D | decode.cc | 114 inst->staticInst, inst->pc, static_inst); 175 decode_info.microopPC = inst->pc; 186 output_inst->pc = decode_info.microopPC;
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H A D | pipe_data.hh | 91 * count it as stream changing itself and expect pc to be the PC 182 * <= pc.instAddr() */ 186 TheISA::PCState pc; member in class:Minor::ForwardLineData 199 /** Line data. line[0] is the byte at address pc.instAddr(). Data is
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/gem5/src/mem/cache/prefetch/ |
H A D | base.cc | 60 : address(addr), pc(pkt->req->hasPC() ? pkt->req->getPC() : 0), 76 : address(addr), pc(pfi.pc), masterId(pfi.masterId), validPC(pfi.validPC),
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/gem5/src/cpu/trace/ |
H A D | trace_cpu.cc | 629 "virt addr %d, pc %#x, size %d, flags %d).\n", 631 node_ptr->pc, node_ptr->size, node_ptr->flags); 661 req->setPC(node_ptr->pc); 666 node_ptr->flags, masterID, node_ptr->pc); 1086 currElement.cmd, currElement.flags, currElement.pc)) { 1138 DPRINTF(TraceCPUInst, "inst fetch: %c addr %d pc %#x size %d tick %d\n", 1141 currElement.pc, 1150 Request::FlagsType flags, Addr pc) 1155 req->setPC(pc); 1350 element->pc 1149 send(Addr addr, unsigned size, const MemCmd& cmd, Request::FlagsType flags, Addr pc) argument [all...] |
H A D | trace_cpu.hh | 369 Addr pc; member in struct:TraceCPU::FixedRetryGen::TraceElement 471 * @param pc instruction PC that generated the request 476 Request::FlagsType flags, Addr pc); 619 Addr pc; member in class:TraceCPU::ElasticDataGen::GraphNode
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/gem5/src/cpu/simple/ |
H A D | base.cc | 144 Addr oldpc, pc = threadInfo[curThread]->thread->instAddr(); local 146 oldpc = pc; 148 pc = threadInfo[curThread]->thread->instAddr(); 149 } while (oldpc != pc); 529 //fetch beyond the MachInst at the current pc. 587 TheISA::PCState pc = threadContexts[curThread]->pcState(); local 588 Addr instAddr = pc.instAddr(); 608 CPA::cpa()->swAutoBegin(threadContexts[curThread], pc.nextInstAddr()); 677 //Since we're moving to a new pc, zero out the offset
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/gem5/src/cpu/o3/ |
H A D | fetch_impl.hh | 129 pc[i] = 0; 337 pc[tid] = cpu->pcState(tid); 365 pc[tid] = cpu->pcState(tid); 604 DefaultFetch<Impl>::fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc) argument 616 } else if (checkInterrupt(pc) && !delayedCommit[tid]) { 637 Request::INST_FETCH, cpu->instMasterId(), pc, 735 TheISA::PCState fetchPC = pc[tid]; 754 tid, fault->name(), pc[tid]); 767 pc[tid] = newPC; 1018 squash(fromCommit->commitInfo[tid].pc, [all...] |
/gem5/ext/mcpat/ |
H A D | xmlParser.cc | 2392 XMLNode *pc; local 2394 pc = dd->pChild + i; 2395 pc->d->pParent = NULL; 2396 pc->d->ref_count--; 2397 pc->emptyTheNode(force); 2716 XMLNode *pc = d->pChild; local 2718 if (xstricmp(pc->d->lpszName, name) == 0) j++; 2719 pc++; 2728 XMLNode *pc = d->pChild + i; local 2730 if (!xstricmp(pc 2756 XMLNode *pc = d->pChild + i; local 2828 XMLNode *pc = d->pChild; local [all...] |
/gem5/src/arch/arm/insts/ |
H A D | sve_macromem.hh | 98 generateDisassembly(Addr pc, const SymbolTable *symtab) const argument 170 generateDisassembly(Addr pc, const SymbolTable *symtab) const argument 242 generateDisassembly(Addr pc, const SymbolTable *symtab) const argument 315 generateDisassembly(Addr pc, const SymbolTable *symtab) const argument 414 generateDisassembly(Addr pc, const SymbolTable *symtab) const argument 518 generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
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H A D | vfp.hh | 897 Addr pc, const SymbolTable *symtab) const override; 914 Addr pc, const SymbolTable *symtab) const override; 932 Addr pc, const SymbolTable *symtab) const override; 950 Addr pc, const SymbolTable *symtab) const override; 969 Addr pc, const SymbolTable *symtab) const override; 988 Addr pc, const SymbolTable *symtab) const override; 1010 Addr pc, const SymbolTable *symtab) const override; 1031 Addr pc, const SymbolTable *symtab) const override; 1053 Addr pc, const SymbolTable *symtab) const override;
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/gem5/src/arch/x86/insts/ |
H A D | static_inst.hh | 91 std::string generateDisassembly(Addr pc,
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/gem5/src/arch/arm/ |
H A D | utility.hh | 337 advancePC(PCState &pc, const StaticInstPtr &inst) argument 339 inst->advancePC(pc);
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