112771Sqtt2@cornell.edu# See LICENSE for license details. 212771Sqtt2@cornell.edu 312771Sqtt2@cornell.edu#***************************************************************************** 412771Sqtt2@cornell.edu# access.S 512771Sqtt2@cornell.edu#----------------------------------------------------------------------------- 612771Sqtt2@cornell.edu# 712771Sqtt2@cornell.edu# Test access-exception behavior. 812771Sqtt2@cornell.edu# 912771Sqtt2@cornell.edu 1012771Sqtt2@cornell.edu#include "riscv_test.h" 1112771Sqtt2@cornell.edu#include "test_macros.h" 1212771Sqtt2@cornell.edu 1312771Sqtt2@cornell.eduRVTEST_RV64M 1412771Sqtt2@cornell.eduRVTEST_CODE_BEGIN 1512771Sqtt2@cornell.edu 1612771Sqtt2@cornell.edu .align 2 1712771Sqtt2@cornell.edu 1812771Sqtt2@cornell.edu # Flipping just the MSB should result in an illegal address for RV64. 1912771Sqtt2@cornell.edu la t2, fail 2012771Sqtt2@cornell.edu li t0, 1 << (__riscv_xlen - 1) 2112771Sqtt2@cornell.edu xor t0, t0, t2 2212771Sqtt2@cornell.edu 2312771Sqtt2@cornell.edu # jalr to an illegal address should commit (hence should write rd). 2412771Sqtt2@cornell.edu # after the pc is set to rs1, an access exception should be raised. 2512771Sqtt2@cornell.edu li TESTNUM, 2 2612771Sqtt2@cornell.edu li t1, CAUSE_FETCH_ACCESS 2712771Sqtt2@cornell.edu la t3, 1f 2812771Sqtt2@cornell.edu li t2, 0 2912771Sqtt2@cornell.edu jalr t2, t0 3012771Sqtt2@cornell.edu1: 3112771Sqtt2@cornell.edu 3212771Sqtt2@cornell.edu # A load to an illegal address should not commit. 3312771Sqtt2@cornell.edu li TESTNUM, 3 3412771Sqtt2@cornell.edu li t1, CAUSE_LOAD_ACCESS 3512771Sqtt2@cornell.edu la t3, 1f 3612771Sqtt2@cornell.edu mv t2, t3 3712771Sqtt2@cornell.edu lb t2, (t0) 3812771Sqtt2@cornell.edu j fail 3912771Sqtt2@cornell.edu1: 4012771Sqtt2@cornell.edu 4112771Sqtt2@cornell.edu j pass 4212771Sqtt2@cornell.edu 4312771Sqtt2@cornell.edu TEST_PASSFAIL 4412771Sqtt2@cornell.edu 4512771Sqtt2@cornell.edu .align 2 4612771Sqtt2@cornell.edu .global mtvec_handler 4712771Sqtt2@cornell.edumtvec_handler: 4812771Sqtt2@cornell.edu li a0, 2 4912771Sqtt2@cornell.edu beq TESTNUM, a0, 2f 5012771Sqtt2@cornell.edu li a0, 3 5112771Sqtt2@cornell.edu beq TESTNUM, a0, 2f 5212771Sqtt2@cornell.edu j fail 5312771Sqtt2@cornell.edu 5412771Sqtt2@cornell.edu2: 5512771Sqtt2@cornell.edu bne t2, t3, fail 5612771Sqtt2@cornell.edu 5712771Sqtt2@cornell.edu csrr t2, mcause 5812771Sqtt2@cornell.edu bne t2, t1, fail 5912771Sqtt2@cornell.edu 6012771Sqtt2@cornell.edu csrw mepc, t3 6112771Sqtt2@cornell.edu mret 6212771Sqtt2@cornell.edu 6312771Sqtt2@cornell.eduRVTEST_CODE_END 6412771Sqtt2@cornell.edu 6512771Sqtt2@cornell.edu .data 6612771Sqtt2@cornell.eduRVTEST_DATA_BEGIN 6712771Sqtt2@cornell.edu 6812771Sqtt2@cornell.edu TEST_DATA 6912771Sqtt2@cornell.edu 7012771Sqtt2@cornell.eduRVTEST_DATA_END 71