Searched refs:pc (Results 151 - 175 of 272) sorted by relevance

1234567891011

/gem5/src/arch/arm/insts/
H A Dmem.cc81 RfeOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
106 SrsOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
H A Dmisc64.cc45 ImmOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
54 RegRegImmImmOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
67 Addr pc, const SymbolTable *symtab) const
81 UnknownOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
338 MiscRegImmOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
350 Addr pc, const SymbolTable *symtab) const
362 Addr pc, const SymbolTable *symtab) const
396 MiscRegImplDefined64::generateDisassembly(Addr pc, argument
66 generateDisassembly( Addr pc, const SymbolTable *symtab) const argument
349 generateDisassembly( Addr pc, const SymbolTable *symtab) const argument
361 generateDisassembly( Addr pc, const SymbolTable *symtab) const argument
H A Dstatic_inst.hh200 Addr pc, const SymbolTable *symtab) const override;
307 PCState pc = xc->pcState(); local
308 pc.instNPC(val);
309 xc->pcState(pc);
349 PCState pc = xc->pcState(); local
350 pc.instIWNPC(val);
351 xc->pcState(pc);
359 PCState pc = xc->pcState(); local
360 pc.instAIWNPC(val);
361 xc->pcState(pc);
[all...]
H A Dpred_inst.hh254 Addr pc, const SymbolTable *symtab) const override;
275 Addr pc, const SymbolTable *symtab) const override;
294 Addr pc, const SymbolTable *symtab) const override;
313 Addr pc, const SymbolTable *symtab) const override;
331 Addr pc, const SymbolTable *symtab) const override;
375 Addr pc, const SymbolTable *symtab) const override;
/gem5/src/arch/x86/insts/
H A Dmicromediaop.hh108 std::string generateDisassembly(Addr pc,
129 std::string generateDisassembly(Addr pc,
H A Dmicroldstop.hh117 std::string generateDisassembly(Addr pc,
151 std::string generateDisassembly(Addr pc,
H A Dmicroop.hh114 std::string generateDisassembly(Addr pc, argument
/gem5/src/cpu/pred/
H A Dtage_sc_l_64KB.hh60 uint16_t gtag(ThreadID tid, Addr pc, int bank) const override;
124 void gUpdates(ThreadID tid, Addr pc, bool taken, BranchInfo* bi,
H A Dstatistical_corrector.hh94 int64_t getLocalHistory(int ordinal, Addr pc) argument
98 return localHistories[idx][getEntry(pc, idx)];
122 unsigned getEntry(Addr pc, unsigned idx) argument
124 return (pc ^ (pc >> shifts[idx])) & (localHistories[idx].size()-1);
259 virtual void gUpdates( ThreadID tid, Addr pc, bool taken, BranchInfo* bi,
H A Dloop_predictor.hh148 * @param instShiftAmt Shift the pc by as many bits
165 * @param pc The unshifted branch PC.
169 * @param instShiftAmt Shift the pc by as many bits (if hashing is not
173 bool getLoop(Addr pc, BranchInfo* bi, bool speculative,
178 * @param pc The unshifted branch PC.
184 void loopUpdate(Addr pc, bool Taken, BranchInfo* bi, bool tage_pred);
216 * @param instShiftAmt Shift the pc by as many bits
217 * @param instShiftAmt Shift the pc by as many bits
/gem5/src/arch/alpha/
H A Dfaults.hh235 Addr pc; member in class:AlphaISA::ItbFault
238 ItbFault(Addr _pc) : pc(_pc) { }
254 ItbPageFault(Addr pc) : ItbFault(pc) { } argument
270 ItbAcvFault(Addr pc) : ItbFault(pc) { } argument
/gem5/src/cpu/o3/
H A Dcommit.hh315 TheISA::PCState pcState(ThreadID tid) { return pc[tid]; }
319 { pc[tid] = val; }
322 Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); }
325 Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); }
328 Addr microPC(ThreadID tid) { return pc[tid].microPC(); }
443 TheISA::PCState pc[Impl::MaxThreads]; member in class:DefaultCommit
H A Dfetch.hh306 bool lookupAndUpdateNextPC(const DynInstPtr &inst, TheISA::PCState &pc);
316 * @param pc The actual PC of the current instruction.
319 bool fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc);
326 checkInterrupt(Addr pc) argument
328 return (interruptPending && (THE_ISA != ALPHA_ISA || !(pc & 0x3)));
438 TheISA::PCState pc[Impl::MaxThreads]; member in class:DefaultFetch
H A Dcomm.hh99 TheISA::PCState pc[Impl::MaxThreads]; member in struct:DefaultIEWDefaultCommit
172 /// The pc of the next instruction to execute. This is the next
175 TheISA::PCState pc; // *F member in struct:TimeBufStruct::commitComm
/gem5/ext/systemc/src/sysc/utils/
H A Dsc_hash.h116 int remove(const void* k, void** pk, void** pc);
122 int lookup(const void* k, void** pc) const;
197 int remove(K k, K* pk, C* pc) argument
199 return sc_phash_base::remove((const void*) k, (void**) pk, (void**) pc);
221 int lookup(K k, C* pc) const
223 return sc_phash_base::lookup((const void*) k, (void**) pc);
302 int remove(K k, K* pk, C* pc) argument
304 return sc_phash_base::remove((const void*) k, (void**) pk, (void**) pc);
314 int lookup(K k, C* pc) const
316 return sc_phash_base::lookup((const void*) k, (void**) pc);
392 remove(const char* k, char** pk, C* pc) argument
[all...]
/gem5/src/arch/riscv/
H A Dfaults.hh218 BreakpointFault(const PCState &pc) argument
219 : RiscvFault("Breakpoint", false, BREAKPOINT), pcState(pc)
222 RegVal trap_value() const override { return pcState.pc(); }
/gem5/src/cpu/minor/
H A Ddyn_inst.cc120 os << inst.id << " pc: 0x"
121 << std::hex << inst.pc.instAddr() << std::dec << " (";
187 id, pc.instAddr(), fault->name());
230 id, pc.instAddr(),
H A Ddyn_inst.hh173 TheISA::PCState pc; member in class:Minor::MinorDynInst
237 pc(TheISA::PCState(0)), fault(fault_),
H A Dfetch1.cc156 Addr aligned_pc = thread.pc.instAddr() & ~((Addr) lineSnap - 1);
165 FetchRequestPtr request = new FetchRequest(*this, request_id, thread.pc);
168 "%s addr: 0x%x pc: %s line_offset: %d request_size: %d\n",
169 request_id, aligned_pc, thread.pc, line_offset, request_size);
175 thread.pc.instAddr());
201 Addr pc_low_bits = thread.pc.instAddr() &
204 thread.pc.set(aligned_pc + request_size + pc_low_bits);
206 thread.pc.set(aligned_pc + request_size);
517 thread.pc = branch.target;
551 line.pc
[all...]
/gem5/src/mem/cache/prefetch/
H A Dbase.hh96 Addr pc; member in class:BasePrefetcher::PrefetchInfo
135 * @return the pc value
140 return pc;
/gem5/src/arch/arm/tracers/
H A Dtarmac_parser.cc708 TarmacParserRecord::printMismatchHeader(inst, pc);
746 ArmISA::PCState pc)
753 << ", PC: 0x" << pc.pc()
754 << ", disasm: " << staticInst->disassemble(pc.pc()) << "]"
803 if (pc.instAddr() != instRecord.addr) {
805 printMismatchHeader(staticInst, pc);
806 outs << "diff> [PC] gem5: 0x" << hex << pc.instAddr()
814 printMismatchHeader(staticInst, pc);
745 printMismatchHeader(const StaticInstPtr staticInst, ArmISA::PCState pc) argument
1090 Addr pc; local
1101 trace >> buf >> pc; local
[all...]
/gem5/src/cpu/
H A Dprofile.hh80 void sample(ProfileNode *node, Addr pc);
/gem5/util/statetrace/arch/arm/
H A Dtracechild.cc165 uint32_t pc = getPC(); local
170 sprintf(obuf, "Initial program counter = 0x%08x\n", pc);
244 uint32_t pc = getPC(); local
264 subsOp = ptrace(PTRACE_PEEKDATA, pid, pc, 0);
/gem5/src/arch/sparc/insts/
H A Dmicro.hh61 Addr pc, const SymbolTable *symtab) const override;
/gem5/src/gpu-compute/
H A Dwavefront.hh66 uint32_t pc; member in struct:ReconvergenceStackEntry
69 * @a pc for the first instruction that will be executed by the wavefront
342 void pushToReconvergenceStack(uint32_t pc, uint32_t rpc,
347 uint32_t pc() const;
355 void pc(uint32_t new_pc);

Completed in 24 milliseconds

1234567891011