Searched refs:override (Results 226 - 250 of 403) sorted by relevance

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/gem5/src/arch/sparc/
H A Dtlb.hh123 void flushAll() override; member in class:SparcISA::TLB
161 void takeOverFrom(BaseTLB *otlb) override {}
164 demapPage(Addr vaddr, uint64_t asn) override
172 const RequestPtr &req, ThreadContext *tc, Mode mode) override; member in class:SparcISA::TLB
175 Translation *translation, Mode mode) override; member in class:SparcISA::TLB
178 ThreadContext *tc, Mode mode) const override; member in class:SparcISA::TLB
184 void serialize(CheckpointOut &cp) const override; member in class:SparcISA::TLB
185 void unserialize(CheckpointIn &cp) override; member in class:SparcISA::TLB
/gem5/src/mem/cache/prefetch/
H A Dirregular_stream_buffer.hh87 void reset() override
129 std::vector<AddrPriority> &addresses) override; member in class:IrregularStreamBufferPrefetcher
H A Dindirect_memory.hh104 void reset() override {
143 void reset() override {
193 std::vector<AddrPriority> &addresses) override; member in class:IndirectMemoryPrefetcher
/gem5/src/mem/
H A Dexternal_master.hh126 PortID idx=InvalidPortID) override; member in class:ExternalMaster
133 void init() override; member in class:ExternalMaster
H A Dexternal_slave.hh132 PortID idx=InvalidPortID) override; member in class:ExternalSlave
139 void init() override; member in class:ExternalSlave
/gem5/src/arch/x86/
H A Dinterrupts.hh200 void init() override; member in class:X86ISA::Interrupts
205 Tick read(PacketPtr pkt) override; member in class:X86ISA::Interrupts
206 Tick write(PacketPtr pkt) override; member in class:X86ISA::Interrupts
208 bool recvResponse(PacketPtr pkt) override; member in class:X86ISA::Interrupts
219 AddrRangeList getAddrRanges() const override; member in class:X86ISA::Interrupts
223 PortID idx=InvalidPortID) override
275 void serialize(CheckpointOut &cp) const override; member in class:X86ISA::Interrupts
276 void unserialize(CheckpointIn &cp) override; member in class:X86ISA::Interrupts
/gem5/ext/pybind11/tests/
H A Dtest_gil_scoped.cpp22 void virtual_func() override {
25 void pure_virtual_func() override {
/gem5/ext/nomali/lib/
H A Dmali_midgard.hh52 void reset() override; member in class:NoMali::MaliMidgard::GPUControlSpec
/gem5/src/gpu-compute/
H A Dbrig_object.hh108 HsaCode* getKernel(const std::string &name) const override; member in class:final
109 HsaCode* getFunction(const std::string &name) const override; member in class:final
111 int numKernels() const override { return kernels.size(); }
113 HsaCode* getKernel(int i) const override { return kernels[i]; }
/gem5/util/systemc/systemc_within_gem5/systemc_simple_object/
H A Dprinter.hh81 end_of_elaboration() override
/gem5/src/cpu/testers/traffic_gen/
H A DPyTrafficGen.py65 @cxxMethod(override=True)
/gem5/src/systemc/core/
H A Dsc_main_fiber.hh65 void main() override; member in class:sc_gem5::ScMainFiber
H A Dsensitivity.hh103 void addToEvent(const ::sc_core::sc_event *e) override; member in class:sc_gem5::DynamicSensitivity
104 void delFromEvent(const ::sc_core::sc_event *e) override; member in class:sc_gem5::DynamicSensitivity
107 Category category() override { return Dynamic; }
118 void addToEvent(const ::sc_core::sc_event *e) override; member in class:sc_gem5::StaticSensitivity
119 void delFromEvent(const ::sc_core::sc_event *e) override; member in class:sc_gem5::StaticSensitivity
122 Category category() override { return Static; }
142 void clear() override { delFromEvent(event); }
158 clear() override
280 bool notifyWork(Event *e) override; member in class:sc_gem5::DynamicSensitivityEventOrList
296 bool notifyWork(Event *e) override; member in class:sc_gem5::DynamicSensitivityEventAndList
[all...]
/gem5/src/systemc/tlm_core/2/quantum/
H A Dglobal_quantum_python.cc39 run(pybind11::module &systemc) override
/gem5/src/arch/sparc/insts/
H A Dbranch.hh54 Addr pc, const SymbolTable *symtab) const override; member in class:SparcISA::Branch
69 Addr pc, const SymbolTable *symtab) const override; member in class:SparcISA::BranchDisp
116 Addr pc, const SymbolTable *symtab) const override; member in class:SparcISA::BranchImm13
/gem5/src/cpu/
H A Dstatic_inst.cc49 execute(ExecContext *xc, Trace::InstRecord *traceData) const override
55 advancePC(TheISA::PCState &pcState) const override
61 generateDisassembly(Addr pc, const SymbolTable *symtab) const override
/gem5/src/sim/
H A Dsim_object.hh134 * checkpoint. However, objects can override loadState() to get
189 DrainState drain() override { return DrainState::Drained; }
214 void serialize(CheckpointOut &cp) const override {};
215 void unserialize(CheckpointIn &cp) override {};
/gem5/src/dev/serial/
H A Dterminal.hh130 uint8_t readData() override; member in class:Terminal
131 void writeData(uint8_t c) override; member in class:Terminal
132 bool dataAvailable() const override { return !rxbuf.empty(); }
/gem5/src/dev/sparc/
H A Diob.hh135 Tick read(PacketPtr pkt) override; member in class:Iob
136 Tick write(PacketPtr pkt) override; member in class:Iob
142 AddrRangeList getAddrRanges() const override; member in class:Iob
144 void serialize(CheckpointOut &cp) const override; member in class:Iob
145 void unserialize(CheckpointIn &cp) override; member in class:Iob
/gem5/src/systemc/tlm_bridge/
H A Dtlm_to_gem5.hh101 recvTimingResp(PacketPtr pkt) override
105 void recvReqRetry() override { bridge.recvReqRetry(); }
106 void recvRangeChange() override { bridge.recvRangeChange(); }
164 ::Port &gem5_getPort(const std::string &if_name, int idx=-1) override; member in class:sc_gem5::TlmToGem5Bridge
175 void before_end_of_elaboration() override; member in class:sc_gem5::TlmToGem5Bridge
/gem5/src/arch/arm/
H A Dtlb.hh219 void takeOverFrom(BaseTLB *otlb) override; member in class:ArmISA::TLB
222 void init() override; member in class:ArmISA::TLB
266 void flushAll() override
311 void demapPage(Addr vaddr, uint64_t asn) override
335 ThreadContext *tc, Mode mode) override
363 ThreadContext *tc, Mode mode) override
373 Translation *translation, Mode mode) override
382 ThreadContext *tc, Mode mode) const override; member in class:ArmISA::TLB
384 void drainResume() override; member in class:ArmISA::TLB
387 void serialize(CheckpointOut &cp) const override; member in class:ArmISA::TLB
388 void unserialize(CheckpointIn &cp) override; member in class:ArmISA::TLB
390 void regStats() override; member in class:ArmISA::TLB
392 void regProbePoints() override; member in class:ArmISA::TLB
404 Port *getTableWalkerPort() override; member in class:ArmISA::TLB
[all...]
/gem5/src/cpu/o3/
H A Dcpu.hh192 void regStats() override; member in class:FullO3CPU
198 void regProbePoints() override; member in class:FullO3CPU
222 void init() override; member in class:FullO3CPU
224 void startup() override; member in class:FullO3CPU
243 Counter totalInsts() const override; member in class:FullO3CPU
246 Counter totalOps() const override; member in class:FullO3CPU
249 void activateContext(ThreadID tid) override; member in class:FullO3CPU
252 void suspendContext(ThreadID tid) override; member in class:FullO3CPU
257 void haltContext(ThreadID tid) override; member in class:FullO3CPU
265 void serializeThread(CheckpointOut &cp, ThreadID tid) const override; member in class:FullO3CPU
266 void unserializeThread(CheckpointIn &cp, ThreadID tid) override; member in class:FullO3CPU
291 DrainState drain() override; member in class:FullO3CPU
294 void drainResume() override; member in class:FullO3CPU
306 void switchOut() override; member in class:FullO3CPU
309 void takeOverFrom(BaseCPU *oldCPU) override; member in class:FullO3CPU
311 void verifyMemoryMode() const override; member in class:FullO3CPU
670 virtual void wakeup(ThreadID tid) override; member in class:FullO3CPU
[all...]
/gem5/src/dev/net/
H A Dsinic.hh74 void serialize(CheckpointOut &cp) const override; member in class:Sinic::Base
75 void unserialize(CheckpointIn &cp) override; member in class:Sinic::Base
234 PortID idx=InvalidPortID) override; member in class:Sinic::Device
263 Tick read(PacketPtr pkt) override; member in class:Sinic::Device
264 Tick write(PacketPtr pkt) override; member in class:Sinic::Device
265 virtual void drainResume() override; member in class:Sinic::Device
284 void regStats() override; member in class:Sinic::Device
285 void resetStats() override; member in class:Sinic::Device
291 void serialize(CheckpointOut &cp) const override; member in class:Sinic::Device
292 void unserialize(CheckpointIn &cp) override; member in class:Sinic::Device
[all...]
/gem5/src/arch/arm/insts/
H A Ddata64.hh61 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::DataXImmOp
77 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::DataXImmOnlyOp
96 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::DataXSRegOp
115 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::DataXERegOp
129 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::DataX1RegOp
145 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::DataX1RegImmOp
162 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::DataX1Reg2ImmOp
177 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::DataX2RegOp
194 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::DataX2RegImmOp
210 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::DataX3RegOp
229 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::DataXCondCompImmOp
247 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::DataXCondCompRegOp
264 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::DataXCondSelOp
[all...]
/gem5/src/dev/pci/
H A Ddevice.hh168 * for normal operations that it does not need to override.
177 * for normal operations that it does not need to override.
203 AddrRangeList getAddrRanges() const override; member in class:PciDevice
216 void serialize(CheckpointOut &cp) const override; member in class:PciDevice
223 void unserialize(CheckpointIn &cp) override; member in class:PciDevice

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