Searched refs:index (Results 151 - 175 of 275) sorted by relevance

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/gem5/src/systemc/ext/dt/bit/
H A Dsc_logic.hh122 unsigned int index = (int)c; local
123 if (index > 127) {
126 index = 127; // aka Log_X
128 return char_to_logic[index];
/gem5/ext/googletest/googletest/src/
H A Dgtest-printers.cc267 for (size_t index = 0; index < len; ++index) {
268 const CharType cur = begin[index];
/gem5/src/python/m5/
H A Dproxy.py136 def getindex(obj, index):
137 if index == None:
140 obj = obj[index]
142 if index != 0:
144 # if index is 0 and item is not subscriptable, just
177 raise TypeError("Proxy object requires integer index")
/gem5/src/arch/arm/tracers/
H A Dtarmac_base.hh107 RegIndex index; member in struct:Trace::TarmacBaseRecord::RegEntry
/gem5/src/mem/cache/prefetch/
H A Dpif.hh138 * The index table is a small cache-like structure that facilitates
141 AssociativeSet<IndexEntry> index; member in class:PIFPrefetcher
146 * history buffer, initiallly set to the pointer taken from the index
/gem5/src/dev/arm/
H A Dsmmu_v3_ptops.cc89 V7LPageTableOps::index(Addr va, unsigned level) const function in class:V7LPageTableOps
183 V8PageTableOps4k::index(Addr va, unsigned level) const function in class:V8PageTableOps4k
281 V8PageTableOps16k::index(Addr va, unsigned level) const function in class:V8PageTableOps16k
379 V8PageTableOps64k::index(Addr va, unsigned level) const function in class:V8PageTableOps64k
/gem5/src/cpu/pred/
H A Dtage_sc_l_8KB.hh57 int gindex_ext(int index, int bank) const override;
H A Dtage_sc_l.hh106 virtual int gindex_ext(int index, int bank) const = 0;
144 virtual bool calcConf(int index) const override;
/gem5/src/cpu/
H A Dbase.hh199 * @param idx ignored index
238 postInterrupt(ThreadID tid, int int_num, int index) argument
240 interrupts[tid]->post(int_num, index);
246 clearInterrupt(ThreadID tid, int int_num, int index) argument
248 interrupts[tid]->clear(int_num, index);
/gem5/src/gpu-compute/
H A Dgpu_tlb.hh264 : SlavePort(_name, gpu_TLB), tlb(gpu_TLB), index(_index) { }
268 int index; member in class:X86ISA::GpuTLB::CpuSidePort
291 : MasterPort(_name, gpu_TLB), tlb(gpu_TLB), index(_index) { }
297 int index; member in class:X86ISA::GpuTLB::MemSidePort
H A Dcompute_unit.cc627 int index = sender_state->port_index; local
673 computeUnit->memPort[index]->createMemRespEvent(pkt);
675 DPRINTF(GPUPort, "CU%d: WF[%d][%d]: index %d, addr %#x received!\n",
677 index, pkt->req->getPaddr());
743 ComputeUnit::sendRequest(GPUDynInstPtr gpuDynInst, int index, PacketPtr pkt) argument
772 int tlbPort_index = perLaneTLB ? index : 0;
797 pkt->senderState = new DTLBPort::SenderState(gpuDynInst, index);
840 index, nullptr);
842 gpuDynInst->memStatusVector[pkt->getAddr()].push_back(index);
843 gpuDynInst->tlbHitLevel[index]
923 sendSyncRequest(GPUDynInstPtr gpuDynInst, int index, PacketPtr pkt) argument
993 int index = gpuDynInst->memStatusVector[paddr].back(); local
[all...]
H A Dcompute_unit.hh110 // TODO: make enum to index readyList
284 void sendRequest(GPUDynInstPtr gpuDynInst, int index, PacketPtr pkt);
285 void sendSyncRequest(GPUDynInstPtr gpuDynInst, int index, PacketPtr pkt);
427 index(_index) { }
454 int index; member in class:ComputeUnit::DataPort
477 index(_index) { }
495 int index; member in class:ComputeUnit::SQCPort
517 index(_index), stalled(false)
550 int index; member in class:ComputeUnit::DTLBPort
H A Dbrig_object.hh105 unsigned getOperandPtr(int offs, int index) const;
/gem5/ext/pybind11/tests/
H A Dtest_sequences_and_iterators.cpp152 float operator[](size_t index) const { return m_data[index]; }
153 float &operator[](size_t index) { return m_data[index]; } argument
286 if (index == seq.size())
288 return seq[index++];
293 size_t index = 0;
/gem5/ext/googletest/googletest/include/gtest/internal/
H A Dgtest-param-util.h57 // Consists of the parameter value and the integer parameter index.
62 index(an_index) {}
64 size_t index; member in struct:testing::TestParamInfo
224 Iterator(const ParamGeneratorInterface<T>* base, T value, int index, argument
226 : base_(base), value_(value), index_(index), step_(step) {}
281 // The index for the end() iterator. All the elements in the generated
375 // integer test parameter index.
379 name_stream << info.index;
521 // parameter index. For the test SequenceA/FooTest.DoBar/1 FooTest is
646 for (std::string::size_type index
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/gem5/src/cpu/o3/
H A Drename_impl.hh980 tid, hb_it->instSeqNum, hb_it->archReg.index(),
981 hb_it->newPhysReg->index(), hb_it->prevPhysReg->index());
1047 tid, hb_it->prevPhysReg->index(),
1105 src_reg.index(), renamed_reg->index(),
1115 tid, renamed_reg->index(), renamed_reg->flatIndex(),
1123 tid, renamed_reg->index(), renamed_reg->flatIndex(),
1156 tid, dest_reg.index(), dest_reg.className(),
1157 rename_result.first->index(),
[all...]
/gem5/src/cpu/checker/
H A Dcpu_impl.hh608 thread->setIntReg(idx.index(), mismatch_val.asInteger());
612 thread->setFloatReg(idx.index(), mismatch_val.asInteger());
625 thread->setCCReg(idx.index(), mismatch_val.asInteger());
629 thread->setMiscReg(idx.index(), mismatch_val.asInteger());
643 thread->setIntReg(idx.index(), res.asInteger());
647 thread->setFloatReg(idx.index(), res.asInteger());
659 thread->setCCReg(idx.index(), res.asInteger());
663 // Try to get the proper misc register index for ARM here...
664 thread->setMiscReg(idx.index(), 0);
H A Dcpu.hh180 // The register accessor methods provide the index of the
182 // register index, to simplify the implementation of register
183 // renaming. We find the architectural register index by indexing
184 // into the instruction's own operand index table. Note that a
196 return thread->readIntReg(reg.index());
204 return thread->readFloatReg(reg.index());
330 return thread->readCCReg(reg.index());
370 thread->setIntReg(reg.index(), val);
379 thread->setFloatReg(reg.index(), val);
388 thread->setCCReg(reg.index(), va
[all...]
/gem5/src/arch/alpha/linux/
H A Dprocess.cc82 int index = 0; local
84 TypedBufferArg<Linux::utsname> name(process->getSyscallArg(tc, index));
102 int index = 0; local
104 unsigned op = process->getSyscallArg(tc, index);
105 Addr bufPtr = process->getSyscallArg(tc, index);
131 int index = 0; local
133 unsigned op = process->getSyscallArg(tc, index);
134 Addr bufPtr = process->getSyscallArg(tc, index);
/gem5/src/mem/ruby/slicc_interface/
H A DAbstractController.hh153 Stats::Histogram& getDelayVCHist(uint32_t index) argument
154 { return *(m_delayVCHistogram[index]); }
/gem5/src/arch/x86/
H A Dinterrupts.hh283 post(int int_num, int index) argument
289 clear(int int_num, int index) argument
H A Dfaults.cc190 for (int index = 0; index < NUM_INTREGS; index++) {
191 tc->setIntReg(index, 0);
/gem5/src/sim/
H A Ddvfs_handler.hh90 DomainID domainID(uint32_t index) const;
/gem5/ext/systemc/src/tlm_utils/
H A Dmulti_socket_bases.h40 , int index \
46 return (tmp_mod->*(tmp_cb->function))(index, TLM_ARG_LIST_WITHOUT_TYPES); \
80 TLM_RET_VAL operator()(int index, TLM_FULL_ARG_LIST){ \
81 return m_fn(m_mod,m_mem_fn, index, TLM_ARG_LIST_WITHOUT_TYPES); \
395 // the key of the map is the index at which the multi initiator i bound, while the value
396 // is the interface of the multi initiator socket that is bound at that index
/gem5/src/arch/mips/
H A Dtlb.hh95 MipsISA::PTE &index(bool advance = true);

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