114039Sstacze01@arm.com/* 214039Sstacze01@arm.com * Copyright (c) 2013, 2018-2019 ARM Limited 314039Sstacze01@arm.com * All rights reserved 414039Sstacze01@arm.com * 514039Sstacze01@arm.com * The license below extends only to copyright in the software and shall 614039Sstacze01@arm.com * not be construed as granting a license to any other intellectual 714039Sstacze01@arm.com * property including but not limited to intellectual property relating 814039Sstacze01@arm.com * to a hardware implementation of the functionality of the software 914039Sstacze01@arm.com * licensed hereunder. You may use the software subject to the license 1014039Sstacze01@arm.com * terms below provided that you ensure that this notice is replicated 1114039Sstacze01@arm.com * unmodified and in its entirety in all distributions of the software, 1214039Sstacze01@arm.com * modified or unmodified, in source code or in binary form. 1314039Sstacze01@arm.com * 1414039Sstacze01@arm.com * Redistribution and use in source and binary forms, with or without 1514039Sstacze01@arm.com * modification, are permitted provided that the following conditions are 1614039Sstacze01@arm.com * met: redistributions of source code must retain the above copyright 1714039Sstacze01@arm.com * notice, this list of conditions and the following disclaimer; 1814039Sstacze01@arm.com * redistributions in binary form must reproduce the above copyright 1914039Sstacze01@arm.com * notice, this list of conditions and the following disclaimer in the 2014039Sstacze01@arm.com * documentation and/or other materials provided with the distribution; 2114039Sstacze01@arm.com * neither the name of the copyright holders nor the names of its 2214039Sstacze01@arm.com * contributors may be used to endorse or promote products derived from 2314039Sstacze01@arm.com * this software without specific prior written permission. 2414039Sstacze01@arm.com * 2514039Sstacze01@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2614039Sstacze01@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2714039Sstacze01@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2814039Sstacze01@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2914039Sstacze01@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3014039Sstacze01@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3114039Sstacze01@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3214039Sstacze01@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3314039Sstacze01@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3414039Sstacze01@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3514039Sstacze01@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3614039Sstacze01@arm.com * 3714039Sstacze01@arm.com * Authors: Stan Czerniawski 3814039Sstacze01@arm.com */ 3914039Sstacze01@arm.com 4014039Sstacze01@arm.com#include "dev/arm/smmu_v3_ptops.hh" 4114039Sstacze01@arm.com 4214039Sstacze01@arm.com#include "base/bitfield.hh" 4314039Sstacze01@arm.com#include "base/logging.hh" 4414039Sstacze01@arm.com 4514039Sstacze01@arm.combool 4614039Sstacze01@arm.comV7LPageTableOps::isValid(pte_t pte, unsigned level) const 4714039Sstacze01@arm.com{ 4814039Sstacze01@arm.com switch (level) { 4914039Sstacze01@arm.com case 1: return pte & 0x1; 5014039Sstacze01@arm.com case 2: return pte & 0x1; 5114039Sstacze01@arm.com case 3: return (pte & 0x1) && (pte & 0x2); 5214039Sstacze01@arm.com default: panic("bad level %d", level); 5314039Sstacze01@arm.com } 5414039Sstacze01@arm.com} 5514039Sstacze01@arm.com 5614039Sstacze01@arm.combool 5714039Sstacze01@arm.comV7LPageTableOps::isLeaf(pte_t pte, unsigned level) const 5814039Sstacze01@arm.com{ 5914039Sstacze01@arm.com switch (level) { 6014039Sstacze01@arm.com case 1: return !(pte & 0x2); 6114039Sstacze01@arm.com case 2: return !(pte & 0x2); 6214039Sstacze01@arm.com case 3: return true; 6314039Sstacze01@arm.com default: panic("bad level %d", level); 6414039Sstacze01@arm.com } 6514039Sstacze01@arm.com} 6614039Sstacze01@arm.com 6714039Sstacze01@arm.combool 6814039Sstacze01@arm.comV7LPageTableOps::isWritable(pte_t pte, unsigned level, bool stage2) const 6914039Sstacze01@arm.com{ 7014039Sstacze01@arm.com return stage2 ? bits(pte, 7, 6)==3 : bits(pte, 7)==0; 7114039Sstacze01@arm.com} 7214039Sstacze01@arm.com 7314039Sstacze01@arm.comAddr 7414039Sstacze01@arm.comV7LPageTableOps::nextLevelPointer(pte_t pte, unsigned level) const 7514039Sstacze01@arm.com{ 7614039Sstacze01@arm.com if (isLeaf(pte, level)) { 7714039Sstacze01@arm.com switch (level) { 7814039Sstacze01@arm.com case 1: return mbits(pte, 39, 30); 7914039Sstacze01@arm.com case 2: return mbits(pte, 39, 21); 8014039Sstacze01@arm.com case 3: return mbits(pte, 39, 12); 8114039Sstacze01@arm.com default: panic("bad level %d", level); 8214039Sstacze01@arm.com } 8314039Sstacze01@arm.com } else { 8414039Sstacze01@arm.com return mbits(pte, 39, 12); 8514039Sstacze01@arm.com } 8614039Sstacze01@arm.com} 8714039Sstacze01@arm.com 8814039Sstacze01@arm.comAddr 8914039Sstacze01@arm.comV7LPageTableOps::index(Addr va, unsigned level) const 9014039Sstacze01@arm.com{ 9114039Sstacze01@arm.com // In theory this should be configurable... 9214039Sstacze01@arm.com const int n = 12; 9314039Sstacze01@arm.com 9414039Sstacze01@arm.com switch (level) { 9514039Sstacze01@arm.com case 1: return bits(va, 26+n, 30) << 3; break; 9614039Sstacze01@arm.com case 2: return bits(va, 29, 21) << 3; break; 9714039Sstacze01@arm.com case 3: return bits(va, 20, 12) << 3; break; 9814039Sstacze01@arm.com default: panic("bad level %d", level); 9914039Sstacze01@arm.com } 10014039Sstacze01@arm.com} 10114039Sstacze01@arm.com 10214039Sstacze01@arm.comAddr 10314039Sstacze01@arm.comV7LPageTableOps::pageMask(pte_t pte, unsigned level) const 10414039Sstacze01@arm.com{ 10514039Sstacze01@arm.com switch (level) { 10614039Sstacze01@arm.com case 1: return ~mask(30); 10714039Sstacze01@arm.com case 2: return ~mask(21); 10814039Sstacze01@arm.com case 3: return bits(pte, 52) ? ~mask(16) : ~mask(12); 10914039Sstacze01@arm.com default: panic("bad level %d", level); 11014039Sstacze01@arm.com } 11114039Sstacze01@arm.com} 11214039Sstacze01@arm.com 11314039Sstacze01@arm.comAddr 11414039Sstacze01@arm.comV7LPageTableOps::walkMask(unsigned level) const 11514039Sstacze01@arm.com{ 11614039Sstacze01@arm.com switch (level) { 11714039Sstacze01@arm.com case 1: return mask(39, 30); 11814039Sstacze01@arm.com case 2: return mask(39, 21); 11914039Sstacze01@arm.com case 3: return mask(39, 12); 12014039Sstacze01@arm.com default: panic("bad level %d", level); 12114039Sstacze01@arm.com } 12214039Sstacze01@arm.com} 12314039Sstacze01@arm.com 12414039Sstacze01@arm.comunsigned 12514100Sgiacomo.travaglini@arm.comV7LPageTableOps::firstLevel(uint8_t tsz) const 12614039Sstacze01@arm.com{ 12714039Sstacze01@arm.com return 1; 12814039Sstacze01@arm.com} 12914039Sstacze01@arm.com 13014039Sstacze01@arm.comunsigned 13114039Sstacze01@arm.comV7LPageTableOps::lastLevel() const 13214039Sstacze01@arm.com{ 13314039Sstacze01@arm.com return 3; 13414039Sstacze01@arm.com} 13514039Sstacze01@arm.com 13614039Sstacze01@arm.combool 13714039Sstacze01@arm.comV8PageTableOps4k::isValid(pte_t pte, unsigned level) const 13814039Sstacze01@arm.com{ 13914039Sstacze01@arm.com switch (level) { 14014039Sstacze01@arm.com case 0: return pte & 0x1; 14114039Sstacze01@arm.com case 1: return pte & 0x1; 14214039Sstacze01@arm.com case 2: return pte & 0x1; 14314039Sstacze01@arm.com case 3: return (pte & 0x1) && (pte & 0x2); 14414039Sstacze01@arm.com default: panic("bad level %d", level); 14514039Sstacze01@arm.com } 14614039Sstacze01@arm.com} 14714039Sstacze01@arm.com 14814039Sstacze01@arm.combool 14914039Sstacze01@arm.comV8PageTableOps4k::isLeaf(pte_t pte, unsigned level) const 15014039Sstacze01@arm.com{ 15114039Sstacze01@arm.com switch (level) { 15214039Sstacze01@arm.com case 0: return false; 15314039Sstacze01@arm.com case 1: return !(pte & 0x2); 15414039Sstacze01@arm.com case 2: return !(pte & 0x2); 15514039Sstacze01@arm.com case 3: return true; 15614039Sstacze01@arm.com default: panic("bad level %d", level); 15714039Sstacze01@arm.com } 15814039Sstacze01@arm.com} 15914039Sstacze01@arm.com 16014039Sstacze01@arm.combool 16114039Sstacze01@arm.comV8PageTableOps4k::isWritable(pte_t pte, unsigned level, bool stage2) const 16214039Sstacze01@arm.com{ 16314039Sstacze01@arm.com return stage2 ? bits(pte, 7, 6)==3 : bits(pte, 7)==0; 16414039Sstacze01@arm.com} 16514039Sstacze01@arm.com 16614039Sstacze01@arm.comAddr 16714039Sstacze01@arm.comV8PageTableOps4k::nextLevelPointer(pte_t pte, unsigned level) const 16814039Sstacze01@arm.com{ 16914039Sstacze01@arm.com if (isLeaf(pte, level)) { 17014039Sstacze01@arm.com switch (level) { 17114039Sstacze01@arm.com // no level 0 here 17214039Sstacze01@arm.com case 1: return mbits(pte, 47, 30); 17314039Sstacze01@arm.com case 2: return mbits(pte, 47, 21); 17414039Sstacze01@arm.com case 3: return mbits(pte, 47, 12); 17514039Sstacze01@arm.com default: panic("bad level %d", level); 17614039Sstacze01@arm.com } 17714039Sstacze01@arm.com } else { 17814039Sstacze01@arm.com return mbits(pte, 47, 12); 17914039Sstacze01@arm.com } 18014039Sstacze01@arm.com} 18114039Sstacze01@arm.com 18214039Sstacze01@arm.comAddr 18314039Sstacze01@arm.comV8PageTableOps4k::index(Addr va, unsigned level) const 18414039Sstacze01@arm.com{ 18514039Sstacze01@arm.com switch (level) { 18614039Sstacze01@arm.com case 0: return bits(va, 47, 39) << 3; break; 18714039Sstacze01@arm.com case 1: return bits(va, 38, 30) << 3; break; 18814039Sstacze01@arm.com case 2: return bits(va, 29, 21) << 3; break; 18914039Sstacze01@arm.com case 3: return bits(va, 20, 12) << 3; break; 19014039Sstacze01@arm.com default: panic("bad level %d", level); 19114039Sstacze01@arm.com } 19214039Sstacze01@arm.com} 19314039Sstacze01@arm.com 19414039Sstacze01@arm.comAddr 19514039Sstacze01@arm.comV8PageTableOps4k::pageMask(pte_t pte, unsigned level) const 19614039Sstacze01@arm.com{ 19714039Sstacze01@arm.com switch (level) { 19814039Sstacze01@arm.com // no level 0 here 19914039Sstacze01@arm.com case 1: return ~mask(30); 20014039Sstacze01@arm.com case 2: return ~mask(21); 20114039Sstacze01@arm.com case 3: return bits(pte, 52) ? ~mask(16) : ~mask(12); 20214039Sstacze01@arm.com default: panic("bad level %d", level); 20314039Sstacze01@arm.com } 20414039Sstacze01@arm.com} 20514039Sstacze01@arm.com 20614039Sstacze01@arm.comAddr 20714039Sstacze01@arm.comV8PageTableOps4k::walkMask(unsigned level) const 20814039Sstacze01@arm.com{ 20914039Sstacze01@arm.com switch (level) { 21014039Sstacze01@arm.com case 0: return mask(47, 39); 21114039Sstacze01@arm.com case 1: return mask(47, 30); 21214039Sstacze01@arm.com case 2: return mask(47, 21); 21314039Sstacze01@arm.com case 3: return mask(47, 12); 21414039Sstacze01@arm.com default: panic("bad level %d", level); 21514039Sstacze01@arm.com } 21614039Sstacze01@arm.com} 21714039Sstacze01@arm.com 21814039Sstacze01@arm.comunsigned 21914100Sgiacomo.travaglini@arm.comV8PageTableOps4k::firstLevel(uint8_t tsz) const 22014039Sstacze01@arm.com{ 22114100Sgiacomo.travaglini@arm.com if (tsz >= 16 && tsz <= 24) return 0; 22214100Sgiacomo.travaglini@arm.com if (tsz >= 25 && tsz <= 33) return 1; 22314100Sgiacomo.travaglini@arm.com if (tsz >= 34 && tsz <= 39) return 2; 22414100Sgiacomo.travaglini@arm.com 22514100Sgiacomo.travaglini@arm.com panic("Unsupported TnSZ: %d\n", tsz); 22614039Sstacze01@arm.com} 22714039Sstacze01@arm.com 22814039Sstacze01@arm.comunsigned 22914039Sstacze01@arm.comV8PageTableOps4k::lastLevel() const 23014039Sstacze01@arm.com{ 23114039Sstacze01@arm.com return 3; 23214039Sstacze01@arm.com} 23314039Sstacze01@arm.com 23414039Sstacze01@arm.combool 23514098Smichiel.vantol@arm.comV8PageTableOps16k::isValid(pte_t pte, unsigned level) const 23614098Smichiel.vantol@arm.com{ 23714098Smichiel.vantol@arm.com switch (level) { 23814098Smichiel.vantol@arm.com case 0: return pte & 0x1; 23914098Smichiel.vantol@arm.com case 1: return pte & 0x1; 24014098Smichiel.vantol@arm.com case 2: return pte & 0x1; 24114098Smichiel.vantol@arm.com case 3: return (pte & 0x1) && (pte & 0x2); 24214098Smichiel.vantol@arm.com default: panic("bad level %d", level); 24314098Smichiel.vantol@arm.com } 24414098Smichiel.vantol@arm.com} 24514098Smichiel.vantol@arm.com 24614098Smichiel.vantol@arm.combool 24714098Smichiel.vantol@arm.comV8PageTableOps16k::isLeaf(pte_t pte, unsigned level) const 24814098Smichiel.vantol@arm.com{ 24914098Smichiel.vantol@arm.com switch (level) { 25014098Smichiel.vantol@arm.com case 0: return false; 25114098Smichiel.vantol@arm.com case 1: return false; 25214098Smichiel.vantol@arm.com case 2: return !(pte & 0x2); 25314098Smichiel.vantol@arm.com case 3: return true; 25414098Smichiel.vantol@arm.com default: panic("bad level %d", level); 25514098Smichiel.vantol@arm.com } 25614098Smichiel.vantol@arm.com} 25714098Smichiel.vantol@arm.com 25814098Smichiel.vantol@arm.combool 25914098Smichiel.vantol@arm.comV8PageTableOps16k::isWritable(pte_t pte, unsigned level, bool stage2) const 26014098Smichiel.vantol@arm.com{ 26114098Smichiel.vantol@arm.com return stage2 ? bits(pte, 7, 6) == 3 : bits(pte, 7) == 0; 26214098Smichiel.vantol@arm.com} 26314098Smichiel.vantol@arm.com 26414098Smichiel.vantol@arm.comAddr 26514098Smichiel.vantol@arm.comV8PageTableOps16k::nextLevelPointer(pte_t pte, unsigned level) const 26614098Smichiel.vantol@arm.com{ 26714098Smichiel.vantol@arm.com if (isLeaf(pte, level)) { 26814098Smichiel.vantol@arm.com switch (level) { 26914098Smichiel.vantol@arm.com // no level 0 here 27014098Smichiel.vantol@arm.com case 1: return mbits(pte, 47, 36); 27114098Smichiel.vantol@arm.com case 2: return mbits(pte, 47, 25); 27214098Smichiel.vantol@arm.com case 3: return mbits(pte, 47, 14); 27314098Smichiel.vantol@arm.com default: panic("bad level %d", level); 27414098Smichiel.vantol@arm.com } 27514098Smichiel.vantol@arm.com } else { 27614098Smichiel.vantol@arm.com return mbits(pte, 47, 12); 27714098Smichiel.vantol@arm.com } 27814098Smichiel.vantol@arm.com} 27914098Smichiel.vantol@arm.com 28014098Smichiel.vantol@arm.comAddr 28114098Smichiel.vantol@arm.comV8PageTableOps16k::index(Addr va, unsigned level) const 28214098Smichiel.vantol@arm.com{ 28314098Smichiel.vantol@arm.com switch (level) { 28414098Smichiel.vantol@arm.com case 0: return bits(va, 47, 47) << 3; break; 28514098Smichiel.vantol@arm.com case 1: return bits(va, 46, 36) << 3; break; 28614098Smichiel.vantol@arm.com case 2: return bits(va, 35, 25) << 3; break; 28714098Smichiel.vantol@arm.com case 3: return bits(va, 24, 14) << 3; break; 28814098Smichiel.vantol@arm.com default: panic("bad level %d", level); 28914098Smichiel.vantol@arm.com } 29014098Smichiel.vantol@arm.com} 29114098Smichiel.vantol@arm.com 29214098Smichiel.vantol@arm.comAddr 29314098Smichiel.vantol@arm.comV8PageTableOps16k::pageMask(pte_t pte, unsigned level) const 29414098Smichiel.vantol@arm.com{ 29514098Smichiel.vantol@arm.com switch (level) { 29614098Smichiel.vantol@arm.com // no level 0 here 29714098Smichiel.vantol@arm.com case 1: return ~mask(36); 29814098Smichiel.vantol@arm.com // 16K granule supports contiguous entries also at L2; - 1G 29914098Smichiel.vantol@arm.com case 2: return bits(pte, 52) ? ~mask(30) : ~mask(25); 30014098Smichiel.vantol@arm.com // as well as at L3; - 2M 30114098Smichiel.vantol@arm.com case 3: return bits(pte, 52) ? ~mask(21) : ~mask(14); 30214098Smichiel.vantol@arm.com default: panic("bad level %d", level); 30314098Smichiel.vantol@arm.com } 30414098Smichiel.vantol@arm.com} 30514098Smichiel.vantol@arm.com 30614098Smichiel.vantol@arm.comAddr 30714098Smichiel.vantol@arm.comV8PageTableOps16k::walkMask(unsigned level) const 30814098Smichiel.vantol@arm.com{ 30914098Smichiel.vantol@arm.com switch (level) { 31014098Smichiel.vantol@arm.com case 0: return ~mask(47); 31114098Smichiel.vantol@arm.com case 1: return ~mask(36); 31214098Smichiel.vantol@arm.com case 2: return ~mask(25); 31314098Smichiel.vantol@arm.com case 3: return ~mask(14); 31414098Smichiel.vantol@arm.com default: panic("bad level %d", level); 31514098Smichiel.vantol@arm.com } 31614098Smichiel.vantol@arm.com} 31714098Smichiel.vantol@arm.com 31814098Smichiel.vantol@arm.comunsigned 31914100Sgiacomo.travaglini@arm.comV8PageTableOps16k::firstLevel(uint8_t tsz) const 32014098Smichiel.vantol@arm.com{ 32114100Sgiacomo.travaglini@arm.com if (tsz == 16) return 0; 32214100Sgiacomo.travaglini@arm.com if (tsz >= 17 && tsz <= 27) return 1; 32314100Sgiacomo.travaglini@arm.com if (tsz >= 28 && tsz <= 38) return 2; 32414100Sgiacomo.travaglini@arm.com if (tsz == 39) return 3; 32514100Sgiacomo.travaglini@arm.com 32614100Sgiacomo.travaglini@arm.com panic("Unsupported TnSZ: %d\n", tsz); 32714098Smichiel.vantol@arm.com} 32814098Smichiel.vantol@arm.com 32914098Smichiel.vantol@arm.comunsigned 33014098Smichiel.vantol@arm.comV8PageTableOps16k::lastLevel() const 33114098Smichiel.vantol@arm.com{ 33214098Smichiel.vantol@arm.com return 3; 33314098Smichiel.vantol@arm.com} 33414098Smichiel.vantol@arm.com 33514098Smichiel.vantol@arm.combool 33614039Sstacze01@arm.comV8PageTableOps64k::isValid(pte_t pte, unsigned level) const 33714039Sstacze01@arm.com{ 33814039Sstacze01@arm.com switch (level) { 33914039Sstacze01@arm.com case 1: return pte & 0x1; 34014039Sstacze01@arm.com case 2: return pte & 0x1; 34114039Sstacze01@arm.com case 3: return (pte & 0x1) && (pte & 0x2); 34214039Sstacze01@arm.com default: panic("bad level %d", level); 34314039Sstacze01@arm.com } 34414039Sstacze01@arm.com} 34514039Sstacze01@arm.com 34614039Sstacze01@arm.combool 34714039Sstacze01@arm.comV8PageTableOps64k::isLeaf(pte_t pte, unsigned level) const 34814039Sstacze01@arm.com{ 34914039Sstacze01@arm.com switch (level) { 35014039Sstacze01@arm.com case 1: return false; 35114039Sstacze01@arm.com case 2: return !(pte & 0x2); 35214039Sstacze01@arm.com case 3: return true; 35314039Sstacze01@arm.com default: panic("bad level %d", level); 35414039Sstacze01@arm.com } 35514039Sstacze01@arm.com} 35614039Sstacze01@arm.com 35714039Sstacze01@arm.combool 35814039Sstacze01@arm.comV8PageTableOps64k::isWritable(pte_t pte, unsigned level, bool stage2) const 35914039Sstacze01@arm.com{ 36014039Sstacze01@arm.com return stage2 ? bits(pte, 7, 6)==3 : bits(pte, 7)==0; 36114039Sstacze01@arm.com} 36214039Sstacze01@arm.com 36314039Sstacze01@arm.comAddr 36414039Sstacze01@arm.comV8PageTableOps64k::nextLevelPointer(pte_t pte, unsigned level) const 36514039Sstacze01@arm.com{ 36614039Sstacze01@arm.com if (isLeaf(pte, level)) { 36714039Sstacze01@arm.com switch (level) { 36814039Sstacze01@arm.com // no level 1 here 36914039Sstacze01@arm.com case 2: return mbits(pte, 47, 29); 37014039Sstacze01@arm.com case 3: return mbits(pte, 47, 16); 37114039Sstacze01@arm.com default: panic("bad level %d", level); 37214039Sstacze01@arm.com } 37314039Sstacze01@arm.com } else { 37414039Sstacze01@arm.com return mbits(pte, 47, 16); 37514039Sstacze01@arm.com } 37614039Sstacze01@arm.com} 37714039Sstacze01@arm.com 37814039Sstacze01@arm.comAddr 37914039Sstacze01@arm.comV8PageTableOps64k::index(Addr va, unsigned level) const 38014039Sstacze01@arm.com{ 38114039Sstacze01@arm.com switch (level) { 38214039Sstacze01@arm.com case 1: return bits(va, 47, 42) << 3; break; 38314039Sstacze01@arm.com case 2: return bits(va, 41, 29) << 3; break; 38414039Sstacze01@arm.com case 3: return bits(va, 28, 16) << 3; break; 38514039Sstacze01@arm.com default: panic("bad level %d", level); 38614039Sstacze01@arm.com } 38714039Sstacze01@arm.com} 38814039Sstacze01@arm.com 38914039Sstacze01@arm.comAddr 39014039Sstacze01@arm.comV8PageTableOps64k::pageMask(pte_t pte, unsigned level) const 39114039Sstacze01@arm.com{ 39214039Sstacze01@arm.com switch (level) { 39314039Sstacze01@arm.com // no level 1 here 39414039Sstacze01@arm.com case 2: return ~mask(29); 39514039Sstacze01@arm.com case 3: return bits(pte, 52) ? ~mask(21) : ~mask(16); 39614039Sstacze01@arm.com default: panic("bad level %d", level); 39714039Sstacze01@arm.com } 39814039Sstacze01@arm.com} 39914039Sstacze01@arm.com 40014039Sstacze01@arm.comAddr 40114039Sstacze01@arm.comV8PageTableOps64k::walkMask(unsigned level) const 40214039Sstacze01@arm.com{ 40314039Sstacze01@arm.com switch (level) { 40414039Sstacze01@arm.com case 1: return mask(47, 42); 40514039Sstacze01@arm.com case 2: return mask(47, 29); 40614039Sstacze01@arm.com case 3: return mask(47, 16); 40714039Sstacze01@arm.com default: panic("bad level %d", level); 40814039Sstacze01@arm.com } 40914039Sstacze01@arm.com} 41014039Sstacze01@arm.com 41114039Sstacze01@arm.comunsigned 41214100Sgiacomo.travaglini@arm.comV8PageTableOps64k::firstLevel(uint8_t tsz) const 41314039Sstacze01@arm.com{ 41414100Sgiacomo.travaglini@arm.com if (tsz >= 12 && tsz <= 21) return 1; 41514100Sgiacomo.travaglini@arm.com if (tsz >= 22 && tsz <= 34) return 2; 41614100Sgiacomo.travaglini@arm.com if (tsz >= 35 && tsz <= 39) return 3; 41714100Sgiacomo.travaglini@arm.com 41814100Sgiacomo.travaglini@arm.com panic("Unsupported TnSZ: %d\n", tsz); 41914039Sstacze01@arm.com} 42014039Sstacze01@arm.com 42114039Sstacze01@arm.comunsigned 42214039Sstacze01@arm.comV8PageTableOps64k::lastLevel() const 42314039Sstacze01@arm.com{ 42414039Sstacze01@arm.com return 3; 42514039Sstacze01@arm.com} 426