Searched refs:fatal (Results 151 - 175 of 220) sorted by relevance
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/gem5/src/cpu/minor/ |
H A D | fetch1.cc | 95 fatal("%s: fetch1LineSnapWidth must be a multiple " 103 fatal("%s: fetch1LineWidth must be a multiple of" 110 fatal("%s: fetch1FetchLimit must be >= 1 (%d)\n", name_,
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H A D | lsq.cc | 1419 fatal("%s: executeMaxAccessesInMemory must be >= 1 (%d)\n", name_, 1424 fatal("%s: executeLSQMaxStoreBufferStoresPerCycle must be" 1429 fatal("%s: executeLSQRequestsQueueSize must be" 1434 fatal("%s: executeLSQTransfersQueueSize must be" 1439 fatal("%s: executeLSQStoreBufferSize must be" 1444 fatal("%s: lineWidth: %d must be a power of 2\n", name(), lineWidth);
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H A D | fetch2.cc | 77 fatal("%s: decodeInputWidth must be >= 1 (%d)\n", name, outputWidth); 80 fatal("%s: fetch2InputBufferSize must be >= 1 (%d)\n", name,
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/gem5/src/arch/x86/ |
H A D | tlb.cc | 67 fatal("TLBs must have a non-zero size.\n"); 501 fatal("TLB size less than the one in checkpoint!");
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/gem5/src/python/m5/ |
H A D | main.py | 216 fatal("Tracing is not enabled. Compile with TRACING_ON") 229 from .util import inform, fatal, panic, isInteractive
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/gem5/src/arch/mips/ |
H A D | tlb.cc | 188 fatal("TLB Insert not yet implemented\n");
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/gem5/src/dev/alpha/ |
H A D | backdoor.cc | 98 fatal("Platform is not Tsunami.\n");
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/gem5/src/mem/ |
H A D | drampower.cc | 159 fatal("Got unexpected data rate %d, should be 1 or 2 or 4\n");
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H A D | bridge.cc | 105 fatal("Both ports of a bridge must be connected.\n");
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H A D | mem_checker_monitor.cc | 73 fatal("Communication monitor is not connected on both sides.\n");
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H A D | serial_link.cc | 113 fatal("Both ports of a serial_link must be connected.\n");
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/gem5/configs/ruby/ |
H A D | MESI_Two_Level.py | 50 fatal("This script requires the MESI_Two_Level protocol to be built.")
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H A D | Ruby.py | 48 from m5.util import addToPath, fatal
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/gem5/configs/common/ |
H A D | CacheConfig.py | 95 fatal("When elastic trace is enabled, do not configure L2 caches.")
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/gem5/src/gpu-compute/ |
H A D | cl_driver.cc | 258 fatal("ClDriver: bad ioctl %d\n", req);
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H A D | hsail_code.hh | 405 fatal("Unknown BrigSegment type.\n");
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/gem5/src/python/m5/util/ |
H A D | fdthelper.py | 127 fatal("Value %d doesn't fit in %d cells" % (value, cells))
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/gem5/src/dev/arm/ |
H A D | smmu_v3_slaveifc.cc | 88 fatal("Slave port is not connected.\n");
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H A D | gpu_nomali.cc | 76 fatal("Unrecognized GPU type: %s (%i)\n",
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H A D | timer_cpulocal.cc | 341 fatal("gem5 ARM Model does not support true watchdog operation!\n");
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/gem5/src/base/ |
H A D | cp_annotate.cc | 109 fatal("Multiple annotation objects found in system"); 122 fatal("Couldn't load symbols from file: %s\n", *i); 511 fatal("Queue %s peeking with not enough bytes available in queue!\n", q); 654 fatal("Queue %s had inconsistancy when doing size queue!\n", q); 1020 fatal("Queue %s dequing with no data available in queue!\n", 1032 fatal("Queue %s dequing with no bytes available in queue!\n", 1041 fatal("Queue %s dequing with nothing in queue!\n",
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/gem5/src/arch/hsail/insts/ |
H A D | pseudo_inst.cc | 92 fatal("Multiple magic instructions per PC not " 176 default: fatal("unrecognized magic instruction: %d\n", op);
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/gem5/src/arch/x86/bios/ |
H A D | intelmp.cc | 116 fatal("Either an MP configuration table or a default configuration " 119 fatal("Both an MP configuration table and a default configuration "
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/gem5/src/arch/arm/ |
H A D | pmu.cc | 75 fatal("The PMU can only accept 31 counters, %d counters requested.\n", 145 fatal("Event with id %d is not probe driven\n", id);
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/gem5/src/arch/riscv/ |
H A D | tlb.cc | 190 fatal("TLB Insert not yet implemented\n");
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Completed in 57 milliseconds
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