Searched refs:fatal (Results 101 - 125 of 220) sorted by relevance

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/gem5/src/sim/power/
H A Dmathexpr_powermodel.cc87 fatal("Failed to evaluate power expressions:\n%s%s%s\n",
/gem5/src/gpu-compute/
H A Dgpu_dyn_inst.hh392 fatal("Unrecognized atomic operation");
413 fatal("%s has bad segment type\n", disassemble());
429 fatal("%s has bad scope type\n", disassemble());
441 fatal("%s has bad memory order\n", disassemble());
/gem5/src/systemc/
H A Dsc_port_wrapper.hh85 fatal("Attempt to bind sc_port %s to incompatible port %s.",
118 // fatal error if peer is neither ScPortWrapper nor ScExportWrapper
/gem5/src/sim/
H A Dsim_object.cc128 fatal("%s does not have any port named %s\n", name(), if_name);
H A Dprocess.cc109 fatal("_pid is too large: %d", _pid);
113 fatal("_pid %d is already used", _pid);
277 fatal("Process %s is not associated with any HW contexts!\n", name());
344 fatal("Maximum stack size exceeded\n");
399 fatal("Syscall %d out of range", callnum);
/gem5/src/dev/arm/
H A Dsmmu_v3_caches.cc159 fatal("SMMUTLB must have at least one entry\n");
162 fatal("SMMUTLB associativity cannot be higher than "
168 fatal("Number of SMMUTLB entries must be divisible "
439 fatal("ARMArchTLB must have at least one entry\n");
442 fatal("ARMArchTLB associativity cannot be higher than "
448 fatal("Number of ARMArchTLB entries must be divisible "
638 fatal("IPACache must have at least one entry\n");
641 fatal("IPACache associativity cannot be higher than "
647 fatal("Number of IPACache entries must be divisible "
818 fatal("ConfigCach
[all...]
H A Dgic_v2m.cc87 fatal("Gicv2m: Frame %d's SPI base (%d) is not in SPI space\n",
/gem5/src/cpu/testers/garnet_synthetic_traffic/
H A DGarnetSyntheticTraffic.cc103 fatal("Unknown Traffic Type: %s!\n", traffic);
146 fatal("%s deadlocked at cycle %d\n", name(), curTick());
242 fatal("Unknown Traffic Type: %s!\n", traffic);
/gem5/src/cpu/minor/
H A Dcpu.cc75 fatal("The Minor model doesn't support checking (yet)\n");
101 fatal("The Minor CPU requires the memory system to be in "
239 fatal("The Minor CPU requires the memory system to be in "
/gem5/src/dev/x86/
H A Di8259.cc275 fatal("Line number %d doesn't exist. The max is %d.\n",
290 fatal("Line number %d doesn't exist. The max is %d.\n",
302 fatal("Line number %d doesn't exist. The max is %d.\n",
/gem5/src/arch/hsail/insts/
H A Dmem.hh200 fatal("Bad ldas register operand type %d\n", regDataType.type);
203 fatal("Bad ldas register operand kind %d\n", regDataType.kind);
282 fatal("LdInst has bad memory order type\n");
302 fatal("LdInst has bad memory scope type\n");
720 fatal("Bad ld register operand type %d\n", tmp.regKind);
723 fatal("Bad ld register operand kind %d\n", tmp.kind);
755 fatal("Bad ld register operand type %d, %d\n",
769 fatal("Bad ld register operand type %d, %d\n",
773 fatal("Bad ld register operand type %d, %d\n", dest.regKind,
850 fatal("StIns
[all...]
H A Ddecl.hh642 fatal("Bad cmpOp value %d\n", (int)cmpOp);
1026 fatal("MemInst has bad BrigMemoryOrder\n");
1059 fatal("MemFence has bad global scope type\n");
1081 fatal("MemFence has bad global scope type\n");
1103 fatal("MemFence has bad group scope type\n");
1106 fatal("MemFence constructor: bad scope specifiers\n");
1146 fatal("MemFence execute: bad op type\n");
1235 fatal("call::exec cannot find function: %s\n", func_name);
1264 fatal("Native HSAIL functions are not yet implemented: %s\n",
/gem5/src/mem/
H A Dxbar.cc338 fatal("Unable to find destination for %s on %s\n", addr_range.to_string(),
378 fatal("Crossbar %s may only have a single default range",
404 fatal("%s has two ports responding within range "
424 fatal("Crossbar %s uses default range, but none provided",
490 fatal("Range %s intersects the " \
/gem5/src/base/loader/
H A Delf_object.cc98 fatal("The binary you're trying to load is compiled for big "
120 fatal("The binary you're trying to load is compiled for "
125 fatal("The binary you're trying to load is compiled for 64-bit "
191 fatal("gem5 does not support the HURD ABI.\n");
247 fatal("Unable to open dynamic executable's interpreter.\n");
328 fatal("Error from libelf: %s.\n", errorMessage);
/gem5/src/cpu/simple/probes/
H A Dsimpoint.cc56 fatal("unable to open SimPoint profile_file");
/gem5/src/base/
H A Dtime.cc165 fatal("Failed to reserve memory for UTC time conversion\n");
/gem5/src/cpu/testers/traffic_gen/
H A Ddram_gen.cc82 fatal("Attempting to use more banks (%d) than "
/gem5/configs/network/
H A DNetwork.py36 from m5.util import addToPath, fatal
/gem5/src/mem/cache/prefetch/
H A Dsbooe.cc46 fatal("%s: the score threshold should be between 0 and 100\n", name());
/gem5/src/systemc/core/
H A Dkernel.cc73 fatal("Simulation called sc_stop during elaboration.\n");
/gem5/configs/example/
H A Dfs.py53 from m5.util import addToPath, fatal, warn
106 fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
197 fatal("SimPoint generation should be done with atomic cpu")
199 fatal("SimPoint generation not supported with more than one CPUs")
/gem5/configs/learning_gem5/part1/
H A Dtwo_level.py81 m5.fatal("Expected a binary to execute as positional argument")
/gem5/src/arch/generic/
H A Ddebugfaults.hh132 void debugFunc() override { fatal(message()); }
133 FaultName name() const override { return "fatal fault"; }
/gem5/src/cpu/o3/
H A Dstore_set.cc46 fatal("Invalid SSIT size!\n");
57 fatal("Invalid LFST size!\n");
/gem5/src/arch/arm/linux/
H A Dsystem.cc138 fatal("couldn't load DTB file: %s\n", params()->dtb_filename);
177 fatal("Expected a single ATAG memory entry but got %d\n",

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