15390SN/A/* 25390SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 35390SN/A * All rights reserved. 45390SN/A * 55390SN/A * Redistribution and use in source and binary forms, with or without 65390SN/A * modification, are permitted provided that the following conditions are 75390SN/A * met: redistributions of source code must retain the above copyright 85390SN/A * notice, this list of conditions and the following disclaimer; 95390SN/A * redistributions in binary form must reproduce the above copyright 105390SN/A * notice, this list of conditions and the following disclaimer in the 115390SN/A * documentation and/or other materials provided with the distribution; 125390SN/A * neither the name of the copyright holders nor the names of its 135390SN/A * contributors may be used to endorse or promote products derived from 145390SN/A * this software without specific prior written permission. 155390SN/A * 165390SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175390SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185390SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195390SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205390SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215390SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225390SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235390SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245390SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255390SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265390SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275390SN/A * 285390SN/A * Authors: Gabe Black 295390SN/A */ 305390SN/A 3111793Sbrandon.potter@amd.com#include "dev/x86/i8259.hh" 3211793Sbrandon.potter@amd.com 335631Sgblack@eecs.umich.edu#include "base/bitfield.hh" 348232Snate@binkert.org#include "debug/I8259.hh" 355657Sgblack@eecs.umich.edu#include "dev/x86/i82094aa.hh" 365698Snate@binkert.org#include "mem/packet.hh" 375698Snate@binkert.org#include "mem/packet_access.hh" 385390SN/A 399808Sstever@gmail.comX86ISA::I8259::I8259(Params * p) 4014290Sgabeblack@google.com : BasicPioDevice(p, 2), 4114290Sgabeblack@google.com latency(p->pio_latency), 429808Sstever@gmail.com mode(p->mode), slave(p->slave), 439808Sstever@gmail.com IRR(0), ISR(0), IMR(0), 449808Sstever@gmail.com readIRR(true), initControlWord(0), autoEOI(false) 455657Sgblack@eecs.umich.edu{ 4614290Sgabeblack@google.com for (int i = 0; i < p->port_output_connection_count; i++) { 4714291Sgabeblack@google.com output.push_back(new IntSourcePin<I8259>( 4814290Sgabeblack@google.com csprintf("%s.output[%d]", name(), i), i, this)); 4914290Sgabeblack@google.com } 5014290Sgabeblack@google.com 5114290Sgabeblack@google.com int in_count = p->port_inputs_connection_count; 5214290Sgabeblack@google.com panic_if(in_count >= NumLines, 5314290Sgabeblack@google.com "I8259 only supports 8 inputs, but there are %d.", in_count); 5414290Sgabeblack@google.com for (int i = 0; i < in_count; i++) { 5514291Sgabeblack@google.com inputs.push_back(new IntSinkPin<I8259>( 5614290Sgabeblack@google.com csprintf("%s.inputs[%d]", name(), i), i, this)); 5714290Sgabeblack@google.com } 5814290Sgabeblack@google.com 5914290Sgabeblack@google.com for (bool &state: pinStates) 6014290Sgabeblack@google.com state = false; 6114290Sgabeblack@google.com} 6214290Sgabeblack@google.com 6314290Sgabeblack@google.comvoid 6414290Sgabeblack@google.comX86ISA::I8259::init() 6514290Sgabeblack@google.com{ 6614290Sgabeblack@google.com BasicPioDevice::init(); 6714290Sgabeblack@google.com 6814290Sgabeblack@google.com for (auto *input: inputs) 6914290Sgabeblack@google.com pinStates[input->getId()] = input->state(); 705657Sgblack@eecs.umich.edu} 715657Sgblack@eecs.umich.edu 725390SN/ATick 735390SN/AX86ISA::I8259::read(PacketPtr pkt) 745390SN/A{ 755631Sgblack@eecs.umich.edu assert(pkt->getSize() == 1); 765631Sgblack@eecs.umich.edu switch(pkt->getAddr() - pioAddr) 775631Sgblack@eecs.umich.edu { 785631Sgblack@eecs.umich.edu case 0x0: 795631Sgblack@eecs.umich.edu if (readIRR) { 805631Sgblack@eecs.umich.edu DPRINTF(I8259, "Reading IRR as %#x.\n", IRR); 8113229Sgabeblack@google.com pkt->setLE(IRR); 825631Sgblack@eecs.umich.edu } else { 835631Sgblack@eecs.umich.edu DPRINTF(I8259, "Reading ISR as %#x.\n", ISR); 8413229Sgabeblack@google.com pkt->setLE(ISR); 855631Sgblack@eecs.umich.edu } 865631Sgblack@eecs.umich.edu break; 875631Sgblack@eecs.umich.edu case 0x1: 885631Sgblack@eecs.umich.edu DPRINTF(I8259, "Reading IMR as %#x.\n", IMR); 8913229Sgabeblack@google.com pkt->setLE(IMR); 905631Sgblack@eecs.umich.edu break; 915631Sgblack@eecs.umich.edu } 925898Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 935630Sgblack@eecs.umich.edu return latency; 945390SN/A} 955390SN/A 965390SN/ATick 975390SN/AX86ISA::I8259::write(PacketPtr pkt) 985390SN/A{ 995631Sgblack@eecs.umich.edu assert(pkt->getSize() == 1); 10013229Sgabeblack@google.com uint8_t val = pkt->getLE<uint8_t>(); 1015631Sgblack@eecs.umich.edu switch (pkt->getAddr() - pioAddr) { 1025631Sgblack@eecs.umich.edu case 0x0: 1035631Sgblack@eecs.umich.edu if (bits(val, 4)) { 1045631Sgblack@eecs.umich.edu DPRINTF(I8259, "Received initialization command word 1.\n"); 1055631Sgblack@eecs.umich.edu IMR = 0; 1065631Sgblack@eecs.umich.edu edgeTriggered = bits(val, 3); 1075631Sgblack@eecs.umich.edu DPRINTF(I8259, "%s triggered mode.\n", 1085631Sgblack@eecs.umich.edu edgeTriggered ? "Edge" : "Level"); 1095631Sgblack@eecs.umich.edu cascadeMode = !bits(val, 1); 1105631Sgblack@eecs.umich.edu DPRINTF(I8259, "%s mode.\n", 1115631Sgblack@eecs.umich.edu cascadeMode ? "Cascade" : "Single"); 1125631Sgblack@eecs.umich.edu expectICW4 = bits(val, 0); 1135688Sgblack@eecs.umich.edu if (!expectICW4) { 1145688Sgblack@eecs.umich.edu autoEOI = false; 1155688Sgblack@eecs.umich.edu } 1165631Sgblack@eecs.umich.edu initControlWord = 1; 1175631Sgblack@eecs.umich.edu DPRINTF(I8259, "Expecting %d more bytes.\n", expectICW4 ? 3 : 2); 1185631Sgblack@eecs.umich.edu } else if (bits(val, 4, 3) == 0) { 1195631Sgblack@eecs.umich.edu DPRINTF(I8259, "Received operation command word 2.\n"); 1205631Sgblack@eecs.umich.edu switch (bits(val, 7, 5)) { 1215631Sgblack@eecs.umich.edu case 0x0: 1225631Sgblack@eecs.umich.edu DPRINTF(I8259, 1235631Sgblack@eecs.umich.edu "Subcommand: Rotate in auto-EOI mode (clear).\n"); 1245631Sgblack@eecs.umich.edu break; 1255631Sgblack@eecs.umich.edu case 0x1: 1265687Sgblack@eecs.umich.edu { 1275687Sgblack@eecs.umich.edu int line = findMsbSet(ISR); 1285687Sgblack@eecs.umich.edu DPRINTF(I8259, "Subcommand: Nonspecific EOI on line %d.\n", 1295687Sgblack@eecs.umich.edu line); 1305687Sgblack@eecs.umich.edu handleEOI(line); 1315687Sgblack@eecs.umich.edu } 1325631Sgblack@eecs.umich.edu break; 1335631Sgblack@eecs.umich.edu case 0x2: 1345631Sgblack@eecs.umich.edu DPRINTF(I8259, "Subcommand: No operation.\n"); 1355631Sgblack@eecs.umich.edu break; 1365631Sgblack@eecs.umich.edu case 0x3: 1375686Sgblack@eecs.umich.edu { 1385686Sgblack@eecs.umich.edu int line = bits(val, 2, 0); 1395686Sgblack@eecs.umich.edu DPRINTF(I8259, "Subcommand: Specific EIO on line %d.\n", 1405686Sgblack@eecs.umich.edu line); 1415686Sgblack@eecs.umich.edu handleEOI(line); 1425686Sgblack@eecs.umich.edu } 1435631Sgblack@eecs.umich.edu break; 1445631Sgblack@eecs.umich.edu case 0x4: 1455631Sgblack@eecs.umich.edu DPRINTF(I8259, "Subcommand: Rotate in auto-EOI mode (set).\n"); 1465631Sgblack@eecs.umich.edu break; 1475631Sgblack@eecs.umich.edu case 0x5: 1485631Sgblack@eecs.umich.edu DPRINTF(I8259, "Subcommand: Rotate on nonspecific EOI.\n"); 1495631Sgblack@eecs.umich.edu break; 1505631Sgblack@eecs.umich.edu case 0x6: 1515631Sgblack@eecs.umich.edu DPRINTF(I8259, "Subcommand: Set priority command.\n"); 1525631Sgblack@eecs.umich.edu DPRINTF(I8259, "Lowest: IRQ%d Highest IRQ%d.\n", 1535631Sgblack@eecs.umich.edu bits(val, 2, 0), (bits(val, 2, 0) + 1) % 8); 1545631Sgblack@eecs.umich.edu break; 1555631Sgblack@eecs.umich.edu case 0x7: 1565631Sgblack@eecs.umich.edu DPRINTF(I8259, "Subcommand: Rotate on specific EOI.\n"); 1575631Sgblack@eecs.umich.edu DPRINTF(I8259, "Lowest: IRQ%d Highest IRQ%d.\n", 1585631Sgblack@eecs.umich.edu bits(val, 2, 0), (bits(val, 2, 0) + 1) % 8); 1595631Sgblack@eecs.umich.edu break; 1605631Sgblack@eecs.umich.edu } 1615631Sgblack@eecs.umich.edu } else if (bits(val, 4, 3) == 1) { 1625631Sgblack@eecs.umich.edu DPRINTF(I8259, "Received operation command word 3.\n"); 1635631Sgblack@eecs.umich.edu if (bits(val, 7)) { 1645631Sgblack@eecs.umich.edu DPRINTF(I8259, "%s special mask mode.\n", 1655631Sgblack@eecs.umich.edu bits(val, 6) ? "Set" : "Clear"); 1665631Sgblack@eecs.umich.edu } 1675631Sgblack@eecs.umich.edu if (bits(val, 1)) { 1685631Sgblack@eecs.umich.edu readIRR = bits(val, 0); 1695631Sgblack@eecs.umich.edu DPRINTF(I8259, "Read %s.\n", readIRR ? "IRR" : "ISR"); 1705631Sgblack@eecs.umich.edu } 1715631Sgblack@eecs.umich.edu } 1725631Sgblack@eecs.umich.edu break; 1735631Sgblack@eecs.umich.edu case 0x1: 1745631Sgblack@eecs.umich.edu switch (initControlWord) { 1755631Sgblack@eecs.umich.edu case 0x0: 1765631Sgblack@eecs.umich.edu DPRINTF(I8259, "Received operation command word 1.\n"); 1775631Sgblack@eecs.umich.edu DPRINTF(I8259, "Wrote IMR value %#x.\n", val); 1785631Sgblack@eecs.umich.edu IMR = val; 1795631Sgblack@eecs.umich.edu break; 1805631Sgblack@eecs.umich.edu case 0x1: 1815631Sgblack@eecs.umich.edu DPRINTF(I8259, "Received initialization command word 2.\n"); 1825656Sgblack@eecs.umich.edu vectorOffset = val & ~mask(3); 1835631Sgblack@eecs.umich.edu DPRINTF(I8259, "Responsible for vectors %#x-%#x.\n", 1845656Sgblack@eecs.umich.edu vectorOffset, vectorOffset | mask(3)); 1855631Sgblack@eecs.umich.edu if (cascadeMode) { 1865631Sgblack@eecs.umich.edu initControlWord++; 1875631Sgblack@eecs.umich.edu } else { 1885632Sgblack@eecs.umich.edu cascadeBits = 0; 1895631Sgblack@eecs.umich.edu initControlWord = 0; 1905631Sgblack@eecs.umich.edu } 1915631Sgblack@eecs.umich.edu break; 1925631Sgblack@eecs.umich.edu case 0x2: 1935631Sgblack@eecs.umich.edu DPRINTF(I8259, "Received initialization command word 3.\n"); 1945634Sgblack@eecs.umich.edu if (mode == Enums::I8259Master) { 1955631Sgblack@eecs.umich.edu DPRINTF(I8259, "Slaves attached to IRQs:%s%s%s%s%s%s%s%s\n", 1965631Sgblack@eecs.umich.edu bits(val, 0) ? " 0" : "", 1975631Sgblack@eecs.umich.edu bits(val, 1) ? " 1" : "", 1985631Sgblack@eecs.umich.edu bits(val, 2) ? " 2" : "", 1995631Sgblack@eecs.umich.edu bits(val, 3) ? " 3" : "", 2005631Sgblack@eecs.umich.edu bits(val, 4) ? " 4" : "", 2015631Sgblack@eecs.umich.edu bits(val, 5) ? " 5" : "", 2025631Sgblack@eecs.umich.edu bits(val, 6) ? " 6" : "", 2035631Sgblack@eecs.umich.edu bits(val, 7) ? " 7" : ""); 2045632Sgblack@eecs.umich.edu cascadeBits = val; 2055631Sgblack@eecs.umich.edu } else { 2065631Sgblack@eecs.umich.edu DPRINTF(I8259, "Slave ID is %d.\n", val & mask(3)); 2075632Sgblack@eecs.umich.edu cascadeBits = val & mask(3); 2085631Sgblack@eecs.umich.edu } 2095631Sgblack@eecs.umich.edu if (expectICW4) 2105631Sgblack@eecs.umich.edu initControlWord++; 2115631Sgblack@eecs.umich.edu else 2125631Sgblack@eecs.umich.edu initControlWord = 0; 2135631Sgblack@eecs.umich.edu break; 2145631Sgblack@eecs.umich.edu case 0x3: 2155631Sgblack@eecs.umich.edu DPRINTF(I8259, "Received initialization command word 4.\n"); 2165631Sgblack@eecs.umich.edu if (bits(val, 4)) { 2175631Sgblack@eecs.umich.edu DPRINTF(I8259, "Special fully nested mode.\n"); 2185631Sgblack@eecs.umich.edu } else { 2195631Sgblack@eecs.umich.edu DPRINTF(I8259, "Not special fully nested mode.\n"); 2205631Sgblack@eecs.umich.edu } 2215631Sgblack@eecs.umich.edu if (bits(val, 3) == 0) { 2225631Sgblack@eecs.umich.edu DPRINTF(I8259, "Nonbuffered.\n"); 2235631Sgblack@eecs.umich.edu } else if (bits(val, 2) == 0) { 2245631Sgblack@eecs.umich.edu DPRINTF(I8259, "Buffered.\n"); 2255631Sgblack@eecs.umich.edu } else { 2265631Sgblack@eecs.umich.edu DPRINTF(I8259, "Unrecognized buffer mode.\n"); 2275631Sgblack@eecs.umich.edu } 2285688Sgblack@eecs.umich.edu autoEOI = bits(val, 1); 2295631Sgblack@eecs.umich.edu DPRINTF(I8259, "%s End Of Interrupt.\n", 2305688Sgblack@eecs.umich.edu autoEOI ? "Automatic" : "Normal"); 2315688Sgblack@eecs.umich.edu 2325631Sgblack@eecs.umich.edu DPRINTF(I8259, "%s mode.\n", bits(val, 0) ? "80x86" : "MCX-80/85"); 2335631Sgblack@eecs.umich.edu initControlWord = 0; 2345631Sgblack@eecs.umich.edu break; 2355631Sgblack@eecs.umich.edu } 2365631Sgblack@eecs.umich.edu break; 2375631Sgblack@eecs.umich.edu } 2385898Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 2395630Sgblack@eecs.umich.edu return latency; 2405390SN/A} 2415630Sgblack@eecs.umich.edu 2425632Sgblack@eecs.umich.eduvoid 2435686Sgblack@eecs.umich.eduX86ISA::I8259::handleEOI(int line) 2445686Sgblack@eecs.umich.edu{ 2455686Sgblack@eecs.umich.edu ISR &= ~(1 << line); 2465686Sgblack@eecs.umich.edu // There may be an interrupt that was waiting which can 2475686Sgblack@eecs.umich.edu // now be sent. 2485686Sgblack@eecs.umich.edu if (IRR) 2495686Sgblack@eecs.umich.edu requestInterrupt(findMsbSet(IRR)); 2505686Sgblack@eecs.umich.edu} 2515686Sgblack@eecs.umich.edu 2525686Sgblack@eecs.umich.eduvoid 2535686Sgblack@eecs.umich.eduX86ISA::I8259::requestInterrupt(int line) 2545686Sgblack@eecs.umich.edu{ 2555686Sgblack@eecs.umich.edu if (bits(ISR, 7, line) == 0) { 25614290Sgabeblack@google.com if (!output.empty()) { 2575686Sgblack@eecs.umich.edu DPRINTF(I8259, "Propogating interrupt.\n"); 25814290Sgabeblack@google.com for (auto *wire: output) { 25914290Sgabeblack@google.com wire->raise(); 26014290Sgabeblack@google.com //XXX This is a hack. 26114290Sgabeblack@google.com wire->lower(); 26214290Sgabeblack@google.com } 2635686Sgblack@eecs.umich.edu } else { 2645686Sgblack@eecs.umich.edu warn("Received interrupt but didn't have " 2655686Sgblack@eecs.umich.edu "anyone to tell about it.\n"); 2665686Sgblack@eecs.umich.edu } 2675686Sgblack@eecs.umich.edu } 2685686Sgblack@eecs.umich.edu} 2695686Sgblack@eecs.umich.edu 2705686Sgblack@eecs.umich.eduvoid 2715632Sgblack@eecs.umich.eduX86ISA::I8259::signalInterrupt(int line) 2725632Sgblack@eecs.umich.edu{ 2735830Sgblack@eecs.umich.edu DPRINTF(I8259, "Interrupt requested for line %d.\n", line); 2745657Sgblack@eecs.umich.edu if (line >= NumLines) 2755657Sgblack@eecs.umich.edu fatal("Line number %d doesn't exist. The max is %d.\n", 2765657Sgblack@eecs.umich.edu line, NumLines - 1); 2775632Sgblack@eecs.umich.edu if (bits(IMR, line)) { 2785632Sgblack@eecs.umich.edu DPRINTF(I8259, "Interrupt %d was masked.\n", line); 2795634Sgblack@eecs.umich.edu } else { 2805657Sgblack@eecs.umich.edu IRR |= 1 << line; 2815686Sgblack@eecs.umich.edu requestInterrupt(line); 2825632Sgblack@eecs.umich.edu } 2835632Sgblack@eecs.umich.edu} 2845632Sgblack@eecs.umich.edu 2855827Sgblack@eecs.umich.eduvoid 2865827Sgblack@eecs.umich.eduX86ISA::I8259::raiseInterruptPin(int number) 2875827Sgblack@eecs.umich.edu{ 2885830Sgblack@eecs.umich.edu DPRINTF(I8259, "Interrupt signal raised for pin %d.\n", number); 2895827Sgblack@eecs.umich.edu if (number >= NumLines) 2905827Sgblack@eecs.umich.edu fatal("Line number %d doesn't exist. The max is %d.\n", 2915827Sgblack@eecs.umich.edu number, NumLines - 1); 2925827Sgblack@eecs.umich.edu if (!pinStates[number]) 2935827Sgblack@eecs.umich.edu signalInterrupt(number); 2945827Sgblack@eecs.umich.edu pinStates[number] = true; 2955827Sgblack@eecs.umich.edu} 2965827Sgblack@eecs.umich.edu 2975827Sgblack@eecs.umich.eduvoid 2985827Sgblack@eecs.umich.eduX86ISA::I8259::lowerInterruptPin(int number) 2995827Sgblack@eecs.umich.edu{ 3005830Sgblack@eecs.umich.edu DPRINTF(I8259, "Interrupt signal lowered for pin %d.\n", number); 3015827Sgblack@eecs.umich.edu if (number >= NumLines) 3025827Sgblack@eecs.umich.edu fatal("Line number %d doesn't exist. The max is %d.\n", 3035827Sgblack@eecs.umich.edu number, NumLines - 1); 3045827Sgblack@eecs.umich.edu pinStates[number] = false; 3055827Sgblack@eecs.umich.edu} 3065827Sgblack@eecs.umich.edu 3075657Sgblack@eecs.umich.eduint 3085657Sgblack@eecs.umich.eduX86ISA::I8259::getVector() 3095657Sgblack@eecs.umich.edu{ 3105657Sgblack@eecs.umich.edu /* 3115657Sgblack@eecs.umich.edu * This code only handles one slave. Since that's how the PC platform 3125657Sgblack@eecs.umich.edu * always uses the 8259 PIC, there shouldn't be any need for more. If 3135657Sgblack@eecs.umich.edu * there -is- a need for more for some reason, "slave" can become a 3145657Sgblack@eecs.umich.edu * vector of slaves. 3155657Sgblack@eecs.umich.edu */ 3165657Sgblack@eecs.umich.edu int line = findMsbSet(IRR); 3175657Sgblack@eecs.umich.edu IRR &= ~(1 << line); 3185657Sgblack@eecs.umich.edu DPRINTF(I8259, "Interrupt %d was accepted.\n", line); 3195688Sgblack@eecs.umich.edu if (autoEOI) { 3205688Sgblack@eecs.umich.edu handleEOI(line); 3215688Sgblack@eecs.umich.edu } else { 3225688Sgblack@eecs.umich.edu ISR |= 1 << line; 3235688Sgblack@eecs.umich.edu } 3245657Sgblack@eecs.umich.edu if (slave && bits(cascadeBits, line)) { 3255657Sgblack@eecs.umich.edu DPRINTF(I8259, "Interrupt was from slave who will " 3265657Sgblack@eecs.umich.edu "provide the vector.\n"); 3275657Sgblack@eecs.umich.edu return slave->getVector(); 3285657Sgblack@eecs.umich.edu } 3295657Sgblack@eecs.umich.edu return line | vectorOffset; 3305657Sgblack@eecs.umich.edu} 3315657Sgblack@eecs.umich.edu 3327903Shestness@cs.utexas.eduvoid 33310905Sandreas.sandberg@arm.comX86ISA::I8259::serialize(CheckpointOut &cp) const 3347903Shestness@cs.utexas.edu{ 3357903Shestness@cs.utexas.edu SERIALIZE_ARRAY(pinStates, NumLines); 3367903Shestness@cs.utexas.edu SERIALIZE_ENUM(mode); 3377903Shestness@cs.utexas.edu SERIALIZE_SCALAR(IRR); 3387903Shestness@cs.utexas.edu SERIALIZE_SCALAR(ISR); 3397903Shestness@cs.utexas.edu SERIALIZE_SCALAR(IMR); 3407903Shestness@cs.utexas.edu SERIALIZE_SCALAR(vectorOffset); 3417903Shestness@cs.utexas.edu SERIALIZE_SCALAR(cascadeMode); 3427903Shestness@cs.utexas.edu SERIALIZE_SCALAR(cascadeBits); 3437903Shestness@cs.utexas.edu SERIALIZE_SCALAR(edgeTriggered); 3447903Shestness@cs.utexas.edu SERIALIZE_SCALAR(readIRR); 3457903Shestness@cs.utexas.edu SERIALIZE_SCALAR(expectICW4); 3467903Shestness@cs.utexas.edu SERIALIZE_SCALAR(initControlWord); 3477903Shestness@cs.utexas.edu SERIALIZE_SCALAR(autoEOI); 3487903Shestness@cs.utexas.edu} 3497903Shestness@cs.utexas.edu 3507903Shestness@cs.utexas.eduvoid 35110905Sandreas.sandberg@arm.comX86ISA::I8259::unserialize(CheckpointIn &cp) 3527903Shestness@cs.utexas.edu{ 3537903Shestness@cs.utexas.edu UNSERIALIZE_ARRAY(pinStates, NumLines); 3547903Shestness@cs.utexas.edu UNSERIALIZE_ENUM(mode); 3557903Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(IRR); 3567903Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(ISR); 3577903Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(IMR); 3587903Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(vectorOffset); 3597903Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(cascadeMode); 3607903Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(cascadeBits); 3617903Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(edgeTriggered); 3627903Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(readIRR); 3637903Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(expectICW4); 3647903Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(initControlWord); 3657903Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(autoEOI); 3667903Shestness@cs.utexas.edu} 3677903Shestness@cs.utexas.edu 3685630Sgblack@eecs.umich.eduX86ISA::I8259 * 3695630Sgblack@eecs.umich.eduI8259Params::create() 3705630Sgblack@eecs.umich.edu{ 3715630Sgblack@eecs.umich.edu return new X86ISA::I8259(this); 3725630Sgblack@eecs.umich.edu} 373