1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#include "dev/x86/i8259.hh"
32
33#include "base/bitfield.hh"
34#include "debug/I8259.hh"
35#include "dev/x86/i82094aa.hh"
36#include "mem/packet.hh"
37#include "mem/packet_access.hh"
38
39X86ISA::I8259::I8259(Params * p)
40    : BasicPioDevice(p, 2),
41      latency(p->pio_latency),
42      mode(p->mode), slave(p->slave),
43      IRR(0), ISR(0), IMR(0),
44      readIRR(true), initControlWord(0), autoEOI(false)
45{
46    for (int i = 0; i < p->port_output_connection_count; i++) {
47        output.push_back(new IntSourcePin<I8259>(
48                    csprintf("%s.output[%d]", name(), i), i, this));
49    }
50
51    int in_count = p->port_inputs_connection_count;
52    panic_if(in_count >= NumLines,
53            "I8259 only supports 8 inputs, but there are %d.", in_count);
54    for (int i = 0; i < in_count; i++) {
55        inputs.push_back(new IntSinkPin<I8259>(
56                    csprintf("%s.inputs[%d]", name(), i), i, this));
57    }
58
59    for (bool &state: pinStates)
60        state = false;
61}
62
63void
64X86ISA::I8259::init()
65{
66    BasicPioDevice::init();
67
68    for (auto *input: inputs)
69        pinStates[input->getId()] = input->state();
70}
71
72Tick
73X86ISA::I8259::read(PacketPtr pkt)
74{
75    assert(pkt->getSize() == 1);
76    switch(pkt->getAddr() - pioAddr)
77    {
78      case 0x0:
79        if (readIRR) {
80            DPRINTF(I8259, "Reading IRR as %#x.\n", IRR);
81            pkt->setLE(IRR);
82        } else {
83            DPRINTF(I8259, "Reading ISR as %#x.\n", ISR);
84            pkt->setLE(ISR);
85        }
86        break;
87      case 0x1:
88        DPRINTF(I8259, "Reading IMR as %#x.\n", IMR);
89        pkt->setLE(IMR);
90        break;
91    }
92    pkt->makeAtomicResponse();
93    return latency;
94}
95
96Tick
97X86ISA::I8259::write(PacketPtr pkt)
98{
99    assert(pkt->getSize() == 1);
100    uint8_t val = pkt->getLE<uint8_t>();
101    switch (pkt->getAddr() - pioAddr) {
102      case 0x0:
103        if (bits(val, 4)) {
104            DPRINTF(I8259, "Received initialization command word 1.\n");
105            IMR = 0;
106            edgeTriggered = bits(val, 3);
107            DPRINTF(I8259, "%s triggered mode.\n",
108                    edgeTriggered ? "Edge" : "Level");
109            cascadeMode = !bits(val, 1);
110            DPRINTF(I8259, "%s mode.\n",
111                    cascadeMode ? "Cascade" : "Single");
112            expectICW4 = bits(val, 0);
113            if (!expectICW4) {
114                autoEOI = false;
115            }
116            initControlWord = 1;
117            DPRINTF(I8259, "Expecting %d more bytes.\n", expectICW4 ? 3 : 2);
118        } else if (bits(val, 4, 3) == 0) {
119            DPRINTF(I8259, "Received operation command word 2.\n");
120            switch (bits(val, 7, 5)) {
121              case 0x0:
122                DPRINTF(I8259,
123                        "Subcommand: Rotate in auto-EOI mode (clear).\n");
124                break;
125              case 0x1:
126                {
127                    int line = findMsbSet(ISR);
128                    DPRINTF(I8259, "Subcommand: Nonspecific EOI on line %d.\n",
129                            line);
130                    handleEOI(line);
131                }
132                break;
133              case 0x2:
134                DPRINTF(I8259, "Subcommand: No operation.\n");
135                break;
136              case 0x3:
137                {
138                    int line = bits(val, 2, 0);
139                    DPRINTF(I8259, "Subcommand: Specific EIO on line %d.\n",
140                            line);
141                    handleEOI(line);
142                }
143                break;
144              case 0x4:
145                DPRINTF(I8259, "Subcommand: Rotate in auto-EOI mode (set).\n");
146                break;
147              case 0x5:
148                DPRINTF(I8259, "Subcommand: Rotate on nonspecific EOI.\n");
149                break;
150              case 0x6:
151                DPRINTF(I8259, "Subcommand: Set priority command.\n");
152                DPRINTF(I8259, "Lowest: IRQ%d   Highest IRQ%d.\n",
153                        bits(val, 2, 0), (bits(val, 2, 0) + 1) % 8);
154                break;
155              case 0x7:
156                DPRINTF(I8259, "Subcommand: Rotate on specific EOI.\n");
157                DPRINTF(I8259, "Lowest: IRQ%d   Highest IRQ%d.\n",
158                        bits(val, 2, 0), (bits(val, 2, 0) + 1) % 8);
159                break;
160            }
161        } else if (bits(val, 4, 3) == 1) {
162            DPRINTF(I8259, "Received operation command word 3.\n");
163            if (bits(val, 7)) {
164                DPRINTF(I8259, "%s special mask mode.\n",
165                        bits(val, 6) ? "Set" : "Clear");
166            }
167            if (bits(val, 1)) {
168                readIRR = bits(val, 0);
169                DPRINTF(I8259, "Read %s.\n", readIRR ? "IRR" : "ISR");
170            }
171        }
172        break;
173      case 0x1:
174        switch (initControlWord) {
175          case 0x0:
176            DPRINTF(I8259, "Received operation command word 1.\n");
177            DPRINTF(I8259, "Wrote IMR value %#x.\n", val);
178            IMR = val;
179            break;
180          case 0x1:
181            DPRINTF(I8259, "Received initialization command word 2.\n");
182            vectorOffset = val & ~mask(3);
183            DPRINTF(I8259, "Responsible for vectors %#x-%#x.\n",
184                    vectorOffset, vectorOffset | mask(3));
185            if (cascadeMode) {
186                initControlWord++;
187            } else {
188                cascadeBits = 0;
189                initControlWord = 0;
190            }
191            break;
192          case 0x2:
193            DPRINTF(I8259, "Received initialization command word 3.\n");
194            if (mode == Enums::I8259Master) {
195                DPRINTF(I8259, "Slaves attached to IRQs:%s%s%s%s%s%s%s%s\n",
196                        bits(val, 0) ? " 0" : "",
197                        bits(val, 1) ? " 1" : "",
198                        bits(val, 2) ? " 2" : "",
199                        bits(val, 3) ? " 3" : "",
200                        bits(val, 4) ? " 4" : "",
201                        bits(val, 5) ? " 5" : "",
202                        bits(val, 6) ? " 6" : "",
203                        bits(val, 7) ? " 7" : "");
204                cascadeBits = val;
205            } else {
206                DPRINTF(I8259, "Slave ID is %d.\n", val & mask(3));
207                cascadeBits = val & mask(3);
208            }
209            if (expectICW4)
210                initControlWord++;
211            else
212                initControlWord = 0;
213            break;
214          case 0x3:
215            DPRINTF(I8259, "Received initialization command word 4.\n");
216            if (bits(val, 4)) {
217                DPRINTF(I8259, "Special fully nested mode.\n");
218            } else {
219                DPRINTF(I8259, "Not special fully nested mode.\n");
220            }
221            if (bits(val, 3) == 0) {
222                DPRINTF(I8259, "Nonbuffered.\n");
223            } else if (bits(val, 2) == 0) {
224                DPRINTF(I8259, "Buffered.\n");
225            } else {
226                DPRINTF(I8259, "Unrecognized buffer mode.\n");
227            }
228            autoEOI = bits(val, 1);
229            DPRINTF(I8259, "%s End Of Interrupt.\n",
230                    autoEOI ? "Automatic" : "Normal");
231
232            DPRINTF(I8259, "%s mode.\n", bits(val, 0) ? "80x86" : "MCX-80/85");
233            initControlWord = 0;
234            break;
235        }
236        break;
237    }
238    pkt->makeAtomicResponse();
239    return latency;
240}
241
242void
243X86ISA::I8259::handleEOI(int line)
244{
245    ISR &= ~(1 << line);
246    // There may be an interrupt that was waiting which can
247    // now be sent.
248    if (IRR)
249        requestInterrupt(findMsbSet(IRR));
250}
251
252void
253X86ISA::I8259::requestInterrupt(int line)
254{
255    if (bits(ISR, 7, line) == 0) {
256        if (!output.empty()) {
257            DPRINTF(I8259, "Propogating interrupt.\n");
258            for (auto *wire: output) {
259                wire->raise();
260                //XXX This is a hack.
261                wire->lower();
262            }
263        } else {
264            warn("Received interrupt but didn't have "
265                    "anyone to tell about it.\n");
266        }
267    }
268}
269
270void
271X86ISA::I8259::signalInterrupt(int line)
272{
273    DPRINTF(I8259, "Interrupt requested for line %d.\n", line);
274    if (line >= NumLines)
275        fatal("Line number %d doesn't exist. The max is %d.\n",
276                line, NumLines - 1);
277    if (bits(IMR, line)) {
278        DPRINTF(I8259, "Interrupt %d was masked.\n", line);
279    } else {
280        IRR |= 1 << line;
281        requestInterrupt(line);
282    }
283}
284
285void
286X86ISA::I8259::raiseInterruptPin(int number)
287{
288    DPRINTF(I8259, "Interrupt signal raised for pin %d.\n", number);
289    if (number >= NumLines)
290        fatal("Line number %d doesn't exist. The max is %d.\n",
291                number, NumLines - 1);
292    if (!pinStates[number])
293        signalInterrupt(number);
294    pinStates[number] = true;
295}
296
297void
298X86ISA::I8259::lowerInterruptPin(int number)
299{
300    DPRINTF(I8259, "Interrupt signal lowered for pin %d.\n", number);
301    if (number >= NumLines)
302        fatal("Line number %d doesn't exist. The max is %d.\n",
303                number, NumLines - 1);
304    pinStates[number] = false;
305}
306
307int
308X86ISA::I8259::getVector()
309{
310    /*
311     * This code only handles one slave. Since that's how the PC platform
312     * always uses the 8259 PIC, there shouldn't be any need for more. If
313     * there -is- a need for more for some reason, "slave" can become a
314     * vector of slaves.
315     */
316    int line = findMsbSet(IRR);
317    IRR &= ~(1 << line);
318    DPRINTF(I8259, "Interrupt %d was accepted.\n", line);
319    if (autoEOI) {
320        handleEOI(line);
321    } else {
322        ISR |= 1 << line;
323    }
324    if (slave && bits(cascadeBits, line)) {
325        DPRINTF(I8259, "Interrupt was from slave who will "
326                "provide the vector.\n");
327        return slave->getVector();
328    }
329    return line | vectorOffset;
330}
331
332void
333X86ISA::I8259::serialize(CheckpointOut &cp) const
334{
335    SERIALIZE_ARRAY(pinStates, NumLines);
336    SERIALIZE_ENUM(mode);
337    SERIALIZE_SCALAR(IRR);
338    SERIALIZE_SCALAR(ISR);
339    SERIALIZE_SCALAR(IMR);
340    SERIALIZE_SCALAR(vectorOffset);
341    SERIALIZE_SCALAR(cascadeMode);
342    SERIALIZE_SCALAR(cascadeBits);
343    SERIALIZE_SCALAR(edgeTriggered);
344    SERIALIZE_SCALAR(readIRR);
345    SERIALIZE_SCALAR(expectICW4);
346    SERIALIZE_SCALAR(initControlWord);
347    SERIALIZE_SCALAR(autoEOI);
348}
349
350void
351X86ISA::I8259::unserialize(CheckpointIn &cp)
352{
353    UNSERIALIZE_ARRAY(pinStates, NumLines);
354    UNSERIALIZE_ENUM(mode);
355    UNSERIALIZE_SCALAR(IRR);
356    UNSERIALIZE_SCALAR(ISR);
357    UNSERIALIZE_SCALAR(IMR);
358    UNSERIALIZE_SCALAR(vectorOffset);
359    UNSERIALIZE_SCALAR(cascadeMode);
360    UNSERIALIZE_SCALAR(cascadeBits);
361    UNSERIALIZE_SCALAR(edgeTriggered);
362    UNSERIALIZE_SCALAR(readIRR);
363    UNSERIALIZE_SCALAR(expectICW4);
364    UNSERIALIZE_SCALAR(initControlWord);
365    UNSERIALIZE_SCALAR(autoEOI);
366}
367
368X86ISA::I8259 *
369I8259Params::create()
370{
371    return new X86ISA::I8259(this);
372}
373