/gem5/src/cpu/ |
H A D | base_dyn_inst.hh | 59 #include "cpu/checker/cpu.hh" 60 #include "cpu/exec_context.hh" 61 #include "cpu/exetrace.hh" 62 #include "cpu/inst_res.hh" 63 #include "cpu/inst_seq.hh" 64 #include "cpu/op_class.hh" 65 #include "cpu/static_inst.hh" 66 #include "cpu/translation.hh" 157 ImplCPU *cpu; member in class:BaseDynInst [all...] |
H A D | thread_state.cc | 31 #include "cpu/thread_state.hh" 34 #include "cpu/base.hh" 35 #include "cpu/profile.hh" 36 #include "cpu/quiesce_event.hh" 46 ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process) argument 48 _status(ThreadContext::Halted), baseCpu(cpu), 111 // itself is created in the base cpu constructor and the
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/gem5/src/dev/alpha/ |
H A D | backdoor.hh | 97 /** a pointer to the CPU boot cpu */ 98 BaseCPU *cpu; member in class:AlphaBackdoor
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/gem5/src/cpu/minor/ |
H A D | pipeline.hh | 50 #include "cpu/minor/activity.hh" 51 #include "cpu/minor/cpu.hh" 52 #include "cpu/minor/decode.hh" 53 #include "cpu/minor/execute.hh" 54 #include "cpu/minor/fetch1.hh" 55 #include "cpu/minor/fetch2.hh" 74 MinorCPU &cpu; member in class:Minor::Pipeline
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H A D | cpu.hh | 49 #include "cpu/minor/activity.hh" 50 #include "cpu/minor/stats.hh" 51 #include "cpu/base.hh" 52 #include "cpu/simple_thread.hh" 59 * pipeline and cpu */ 103 /** The enclosing cpu */ 104 MinorCPU &cpu; member in class:MinorCPU::MinorCPUPort 108 : MasterPort(name_, &cpu_), cpu(cpu_)
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H A D | lsq.cc | 40 #include "cpu/minor/lsq.hh" 48 #include "cpu/minor/cpu.hh" 49 #include "cpu/minor/exec_context.hh" 50 #include "cpu/minor/execute.hh" 51 #include "cpu/minor/pipeline.hh" 52 #include "cpu/utils.hh" 80 SimpleThread &thread = *port.cpu.threads[inst->id.threadId]; 82 ExecContext context(port.cpu, thread, port.execute, inst); 102 SimpleThread &thread = *port.cpu [all...] |
H A D | fetch2.cc | 40 #include "cpu/minor/fetch2.hh" 46 #include "cpu/minor/pipeline.hh" 47 #include "cpu/pred/bpred_unit.hh" 64 cpu(cpu_), 267 for (ThreadID tid = 0; tid < cpu.numThreads; tid++) { 314 ThreadContext *thread = cpu.getContext(line_in->id.threadId); 547 cpu.activityRecorder->activity(); 554 for (ThreadID i = 0; i < cpu.numThreads; i++) 557 cpu.activityRecorder->activateStage(Pipeline::Fetch2StageId); 573 switch (cpu [all...] |
H A D | fetch1.hh | 50 #include "cpu/minor/buffers.hh" 51 #include "cpu/minor/cpu.hh" 52 #include "cpu/minor/pipe_data.hh" 53 #include "cpu/base.hh" 72 IcachePort(std::string name, Fetch1 &fetch_, MinorCPU &cpu) : argument 73 MinorCPU::MinorCPUPort(name, cpu), fetch(fetch_) 192 MinorCPU &cpu; member in class:Minor::Fetch1
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/gem5/src/arch/mips/ |
H A D | MipsSystem.py | 53 boot_cpu_frequency = Param.Frequency(Self.cpu[0].clk_domain.clock[0]
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H A D | utility.cc | 40 #include "cpu/static_inst.hh" 41 #include "cpu/thread_context.hh" 222 zeroRegisters(CPU *cpu) argument 226 // cpu model. Consider changing later.) 227 cpu->thread->setIntReg(ZeroReg, 0); 228 cpu->thread->setFloatReg(ZeroReg, 0);
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/gem5/src/dev/arm/ |
H A D | base_gic.hh | 89 * @param cpu CPU to forward interrupt to 91 virtual void sendPPInt(uint32_t num, uint32_t cpu) = 0; 92 virtual void clearPPInt(uint32_t num, uint32_t cpu) = 0;
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H A D | gic_v2.hh | 55 #include "cpu/intr_control.hh" 93 // cpu memory addresses 107 GICC_IIDR = 0xfc, // cpu interface id register 160 /** Latency for a cpu operation */ 268 /** read only running priority register, 1 per cpu*/ 297 * an 8 bit cpu target id for each global interrupt. 340 * signaled as a FIQ to the cpu. It does that by reading: 374 uint8_t getCpuPriority(unsigned cpu); // BPR-adjusted priority value 382 /** One bit per cpu per software interrupt that is pending for each 383 * possible sgi source. Indexed by SGI number. Each byte in generating cpu [all...] |
H A D | vgic.hh | 60 #include "cpu/intr_control.hh" 109 void processPostVIntEvent(uint32_t cpu); 217 void postVInt(uint32_t cpu, Tick when); 218 void unPostVInt(uint32_t cpu); 219 void postMaintInt(uint32_t cpu); 220 void unPostMaintInt(uint32_t cpu);
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/gem5/src/gpu-compute/ |
H A D | dispatcher.hh | 84 BaseCPU *cpu; member in class:GpuDispatcher 110 void accessUserVar(BaseCPU *cpu, uint64_t addr, int val, int off);
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/gem5/configs/splash2/ |
H A D | run.py | 199 system = System(cpu = cpus, physmem = SimpleMemory(), 218 for cpu in cpus: 219 cpu.addPrivateSplitL1Caches(L1(size = options.l1size, assoc = 1), 221 # connect cpu level-1 caches to shared level-2 cache 222 cpu.connectAllPorts(system.toL2bus, system.membus) 269 for cpu in cpus: 270 cpu.workload = root.workload
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H A D | cluster.py | 213 system = System(cpu = all_cpus, l1_ = all_l1s, l1bus_ = all_l1buses, 235 for cpu in cluster.cpus: 236 cpu.icache_port = cluster.clusterbus.slave 237 cpu.dcache_port = cluster.clusterbus.slave 284 for cpu in cluster.cpus: 285 cpu.workload = root.workload
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/gem5/src/cpu/o3/ |
H A D | iew_impl.hh | 55 #include "cpu/checker/cpu.hh" 56 #include "cpu/o3/fu_pool.hh" 57 #include "cpu/o3/iew.hh" 58 #include "cpu/timebuf.hh" 70 cpu(_cpu), 86 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 90 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 94 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 121 return cpu [all...] |
H A D | lsq_unit_impl.hh | 53 #include "cpu/checker/cpu.hh" 54 #include "cpu/o3/lsq.hh" 55 #include "cpu/o3/lsq_unit.hh" 77 assert(!lsqPtr->cpu->switchedOut()); 118 cpu->ppDataAccessComplete->notify(std::make_pair(inst, pkt)); 124 assert(!cpu->switchedOut()); 161 cpu = cpu_ptr; 190 cacheBlockMask = ~(cpu->cacheLineSize() - 1); 378 for (int x = 0; x < cpu [all...] |
/gem5/src/arch/alpha/ |
H A D | interrupts.hh | 41 #include "cpu/thread_context.hh" 55 BaseCPU * cpu; member in class:AlphaISA::Interrupts 70 Interrupts(Params * p) : SimObject(p), cpu(NULL) 80 cpu = _cpu;
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/gem5/configs/example/ |
H A D | ruby_mem_test.py | 109 system = System(cpu = cpus, 146 for (i, cpu) in enumerate(cpus): 148 # Tie the cpu memtester ports to the correct system ports 150 cpu.port = system.ruby._cpu_ports[i].slave
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H A D | ruby_direct_test.py | 103 system.cpu = RubyDirectedTester(requests_to_complete = options.requests, 116 # Tie the ruby tester ports to the ruby cpu ports 118 system.cpu.cpuPort = ruby_port.slave
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/gem5/configs/example/arm/ |
H A D | starter_se.py | 115 *cpu_types[args.cpu]) 179 for cpu, workload in zip(system.cpu_cluster.cpus, processes): 180 cpu.workload = workload 190 parser.add_argument("--cpu", type=str, choices=cpu_types.keys(), 193 parser.add_argument("--cpu-freq", type=str, default="4GHz")
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/gem5/src/arch/sparc/ |
H A D | interrupts.hh | 38 #include "cpu/thread_context.hh" 61 BaseCPU * cpu; member in class:SparcISA::Interrupts 71 cpu = _cpu; 82 Interrupts(Params * p) : SimObject(p), cpu(NULL)
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/gem5/util/dist/test/ |
H A D | test-2nodes-AArch64.sh | 73 --cpu-type=atomic \
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/gem5/src/arch/arm/kvm/ |
H A D | gic.hh | 45 #include "cpu/kvm/device.hh" 46 #include "cpu/kvm/vm.hh" 142 * Get value of GIC register "from" a cpu 151 * Set value of GIC register "from" a cpu 189 void sendPPInt(uint32_t num, uint32_t cpu) override; 190 void clearPPInt(uint32_t num, uint32_t cpu) override;
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