1/*
2 * Copyright (c) 2013,2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Matt Evans
38 */
39
40
41/** @file
42 * Implementiation of a GIC-400 List Register-based VGIC interface.
43 * The VGIC is, in this implementation, completely separate from the GIC itself.
44 * Only a VIRQ line to the CPU and a PPI line to the GIC (for a HV maintenance IRQ)
45 * is required.
46 *
47 * The mode in which the List Registers may flag (via LR.HW) that a hardware EOI
48 * is to be performed is NOT supported.  (This requires tighter integration with
49 * the GIC.)
50 */
51
52#ifndef __DEV_ARM_VGIC_H__
53#define __DEV_ARM_VGIC_H__
54
55#include <algorithm>
56#include <array>
57
58#include "base/addr_range.hh"
59#include "base/bitunion.hh"
60#include "cpu/intr_control.hh"
61#include "dev/io_device.hh"
62#include "dev/platform.hh"
63#include "params/VGic.hh"
64
65class VGic : public PioDevice
66{
67  private:
68    static const int VGIC_CPU_MAX       = 256;
69    static const int NUM_LR             = 4;
70
71    static const int GICH_SIZE          = 0x200;
72    static const int GICH_REG_SIZE      = 0x2000;
73
74    static const int GICH_HCR           = 0x000;
75    static const int GICH_VTR           = 0x004;
76    static const int GICH_VMCR          = 0x008;
77    static const int GICH_MISR          = 0x010;
78    static const int GICH_EISR0         = 0x020;
79    static const int GICH_EISR1         = 0x024;
80    static const int GICH_ELSR0         = 0x030;
81    static const int GICH_ELSR1         = 0x034;
82    static const int GICH_APR0          = 0x0f0;
83    static const int GICH_LR0           = 0x100;
84    static const int GICH_LR1           = 0x104;
85    static const int GICH_LR2           = 0x108;
86    static const int GICH_LR3           = 0x10c;
87
88    static const int GICV_SIZE          = 0x2000;
89    static const int GICV_CTLR          = 0x000;
90    static const int GICV_PMR           = 0x004;
91    static const int GICV_BPR           = 0x008;
92    static const int GICV_IAR           = 0x00c;
93    static const int GICV_EOIR          = 0x010;
94    static const int GICV_RPR           = 0x014;
95    static const int GICV_HPPIR         = 0x018;
96    static const int GICV_ABPR          = 0x01c;
97    static const int GICV_AIAR          = 0x020;
98    static const int GICV_AEOIR         = 0x024;
99    static const int GICV_AHPPIR        = 0x028;
100    static const int GICV_APR0          = 0x0d0;
101    static const int GICV_IIDR          = 0x0fc;
102    static const int GICV_DIR           = 0x1000;
103
104    static const uint32_t LR_PENDING    = 1;
105    static const uint32_t LR_ACTIVE     = 2;
106    const uint32_t gicvIIDR;
107
108    /** Post interrupt to CPU */
109    void processPostVIntEvent(uint32_t cpu);
110
111    EventFunctionWrapper *postVIntEvent[VGIC_CPU_MAX];
112    bool        maintIntPosted[VGIC_CPU_MAX];
113    bool        vIntPosted[VGIC_CPU_MAX];
114
115    Platform *platform;
116    BaseGic *gic;
117
118    Addr vcpuAddr;
119    Addr hvAddr;
120    Tick pioDelay;
121    int maintInt;
122
123    BitUnion32(ListReg)
124    Bitfield<31> HW;
125    Bitfield<30> Grp1;
126    Bitfield<29,28> State;
127    Bitfield<27,23> Priority;
128    Bitfield<19> EOI;
129    Bitfield<12,10> CpuID;
130    Bitfield<9,0> VirtualID;
131    EndBitUnion(ListReg)
132
133    BitUnion32(HCR)
134    Bitfield<31,27> EOICount;
135    Bitfield<7> VGrp1DIE;
136    Bitfield<6> VGrp1EIE;
137    Bitfield<5> VGrp0DIE;
138    Bitfield<4> VGrp0EIE;
139    Bitfield<3> NPIE;
140    Bitfield<2> LRENPIE;
141    Bitfield<1> UIE;
142    Bitfield<0> En;
143    EndBitUnion(HCR)
144
145    BitUnion32(VCTLR)
146    Bitfield<9> EOImode;
147    Bitfield<4> CPBR;
148    Bitfield<3> FIQEn;
149    Bitfield<2> AckCtl;
150    Bitfield<1> EnGrp1;
151    Bitfield<0> En;     // This gets written to enable, not group 1.
152    EndBitUnion(VCTLR)
153
154    /* State per CPU.  EVERYTHING should be in this struct and simply replicated
155     * N times.
156     */
157    struct vcpuIntData : public Serializable {
158        vcpuIntData()
159            : vctrl(0), hcr(0), eisr(0), VMGrp0En(0), VMGrp1En(0),
160              VMAckCtl(0), VMFiqEn(0), VMCBPR(0), VEM(0), VMABP(0), VMBP(0),
161              VMPriMask(0)
162        {
163            std::fill(LR.begin(), LR.end(), 0);
164        }
165        virtual ~vcpuIntData() {}
166
167        std::array<ListReg, NUM_LR> LR;
168        VCTLR vctrl;
169
170        HCR hcr;
171        uint64_t eisr;
172
173        /* Host info, guest info (should be 100% accessible via GICH_* regs!) */
174        uint8_t VMGrp0En;
175        uint8_t VMGrp1En;
176        uint8_t VMAckCtl;
177        uint8_t VMFiqEn;
178        uint8_t VMCBPR;
179        uint8_t VEM;
180        uint8_t VMABP;
181        uint8_t VMBP;
182        uint8_t VMPriMask;
183
184        void serialize(CheckpointOut &cp) const override;
185        void unserialize(CheckpointIn &cp) override;
186    };
187
188    struct std::array<vcpuIntData, VGIC_CPU_MAX>  vcpuData;
189
190  public:
191   typedef VGicParams Params;
192   const Params *
193    params() const
194    {
195        return dynamic_cast<const Params *>(_params);
196    }
197    VGic(const Params *p);
198    ~VGic();
199
200    AddrRangeList getAddrRanges() const override;
201
202    Tick read(PacketPtr pkt) override;
203    Tick write(PacketPtr pkt) override;
204
205    void serialize(CheckpointOut &cp) const override;
206    void unserialize(CheckpointIn &cp) override;
207
208  private:
209    Tick readVCpu(PacketPtr pkt);
210    Tick readCtrl(PacketPtr pkt);
211
212    Tick writeVCpu(PacketPtr pkt);
213    Tick writeCtrl(PacketPtr pkt);
214
215    void updateIntState(ContextID ctx_id);
216    uint32_t getMISR(struct vcpuIntData *vid);
217    void postVInt(uint32_t cpu, Tick when);
218    void unPostVInt(uint32_t cpu);
219    void postMaintInt(uint32_t cpu);
220    void unPostMaintInt(uint32_t cpu);
221
222    unsigned int lrPending(struct vcpuIntData *vid)
223    {
224        unsigned int pend = 0;
225        for (int i = 0; i < NUM_LR; i++) {
226            if (vid->LR[i].State & LR_PENDING)
227                pend++;
228        }
229        return pend;
230    }
231    unsigned int lrValid(struct vcpuIntData *vid)
232    {
233        unsigned int valid = 0;
234        for (int i = 0; i < NUM_LR; i++) {
235            if (vid->LR[i].State)
236                valid++;
237        }
238        return valid;
239    }
240
241    /** Returns LR index or -1 if none pending */
242    int findHighestPendingLR(struct vcpuIntData *vid)
243    {
244        unsigned int prio = 0xff;
245        int p = -1;
246        for (int i = 0; i < NUM_LR; i++) {
247            if ((vid->LR[i].State & LR_PENDING) && (vid->LR[i].Priority < prio)) {
248                p = i;
249                prio = vid->LR[i].Priority;
250            }
251        }
252        return p;
253    }
254
255    int findLRForVIRQ(struct vcpuIntData *vid, int virq, int vcpu)
256    {
257        for (int i = 0; i < NUM_LR; i++) {
258            if (vid->LR[i].State &&
259                vid->LR[i].VirtualID == virq &&
260                vid->LR[i].CpuID == vcpu)
261                return i;
262        }
263        return -1;
264    }
265};
266
267#endif
268