Lines Matching refs:cpu
55 #include "cpu/intr_control.hh"
93 // cpu memory addresses
107 GICC_IIDR = 0xfc, // cpu interface id register
160 /** Latency for a cpu operation */
268 /** read only running priority register, 1 per cpu*/
297 * an 8 bit cpu target id for each global interrupt.
340 * signaled as a FIQ to the cpu. It does that by reading:
374 uint8_t getCpuPriority(unsigned cpu); // BPR-adjusted priority value
382 /** One bit per cpu per software interrupt that is pending for each
383 * possible sgi source. Indexed by SGI number. Each byte in generating cpu
415 uint64_t genSwiMask(int cpu);
420 /** Clears a cpu IRQ or FIQ signal */
426 void postInt(uint32_t cpu, Tick when);
427 void postFiq(uint32_t cpu, Tick when);
432 void postDelayedInt(uint32_t cpu);
433 void postDelayedFiq(uint32_t cpu);
472 void sendPPInt(uint32_t num, uint32_t cpu) override;
473 void clearPPInt(uint32_t num, uint32_t cpu) override;
486 /** Handle a read to the cpu portion of the GIC
503 /** Handle a write to the cpu portion of the GIC