/gem5/src/cpu/o3/ |
H A D | scoreboard.hh | 57 const std::string _name; member in class:Scoreboard 78 std::string name() const { return _name; };
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/gem5/src/gpu-compute/ |
H A D | local_memory_pipeline.hh | 79 const std::string& name() const { return _name; } 90 std::string _name; member in class:LocalMemPipeline
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H A D | scoreboard_check_stage.hh | 73 const std::string& name() const { return _name; } 103 std::string _name; member in class:ScoreboardCheckStage
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H A D | tlb_coalescer.hh | 158 CpuSidePort(const std::string &_name, TLBCoalescer *tlb_coalescer, argument 160 : SlavePort(_name, tlb_coalescer), coalescer(tlb_coalescer), 185 MemSidePort(const std::string &_name, TLBCoalescer *tlb_coalescer, argument 187 : MasterPort(_name, tlb_coalescer), coalescer(tlb_coalescer),
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H A D | vector_register_state.hh | 56 const std::string& name() const { return _name; } 94 std::string _name; member in class:VecRegisterState
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H A D | condition_register_state.hh | 55 const std::string name() const { return _name; } 94 std::string _name; member in class:ConditionRegisterState
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/gem5/src/sim/ |
H A D | init.hh | 86 EmbeddedPyBind(const char *_name, 90 EmbeddedPyBind(const char *_name,
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/gem5/src/sim/probe/ |
H A D | probe.cc | 45 ProbePoint::ProbePoint(ProbeManager *manager, const std::string& _name) argument 46 : name(_name) 67 ProbeListener::ProbeListener(ProbeManager *_manager, const std::string &_name) argument 68 : manager(_manager), name(_name)
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/gem5/src/systemc/ext/channel/ |
H A D | sc_signal.hh | 62 ScSignalBase(const char *_name); 82 ScSignalBaseBinary(const char *_name); 108 ScSignalBasePicker(const char *_name) : ScSignalBase(_name) {} argument 115 ScSignalBasePicker(const char *_name) : ScSignalBaseBinary(_name) {} argument 122 ScSignalBasePicker(const char *_name) : ScSignalBaseBinary(_name) {} argument 166 ScSignalBaseT(const char *_name) : argument 167 ScSignalBasePicker<T>(_name), m_cur_va 170 ScSignalBaseT(const char *_name, const T &initial_value) argument 247 ScSignalBinary(const char *_name) argument 249 ScSignalBinary(const char *_name, const T& initial_value) argument [all...] |
/gem5/src/mem/ |
H A D | noncoherent_xbar.hh | 99 NoncoherentXBarSlavePort(const std::string &_name, argument 101 : QueuedSlavePort(_name, &_xbar, queue, _id), xbar(_xbar), 152 NoncoherentXBarMasterPort(const std::string &_name, argument 154 : MasterPort(_name, &_xbar, _id), xbar(_xbar)
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H A D | physical.hh | 118 std::string _name; member in class:PhysicalMemory 161 PhysicalMemory(const std::string& _name, 174 const std::string name() const { return _name; }
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H A D | page_table.hh | 71 const std::string _name; member in class:EmulationPageTable 78 _pid(_pid), _name(__name), shared(false) 105 const std::string name() const { return _name; }
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H A D | addr_mapper.hh | 108 MapperMasterPort(const std::string& _name, AddrMapper& _mapper) argument 109 : MasterPort(_name, &_mapper), mapper(_mapper) 163 MapperSlavePort(const std::string& _name, AddrMapper& _mapper) argument 164 : SlavePort(_name, &_mapper), mapper(_mapper)
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H A D | mem_checker_monitor.hh | 100 MonitorMasterPort(const std::string& _name, MemCheckerMonitor& _mon) argument 101 : MasterPort(_name, &_mon), mon(_mon) 161 MonitorSlavePort(const std::string& _name, MemCheckerMonitor& _mon) argument 162 : SlavePort(_name, &_mon), mon(_mon)
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/gem5/src/dev/x86/ |
H A D | intdev.hh | 64 IntSlavePort(const std::string& _name, SimObject* _parent, argument 66 SimpleTimingPort(_name, _parent), device(dev) 99 IntMasterPort(const std::string& _name, SimObject* _parent, argument 101 QueuedMasterPort(_name, _parent, reqQueue, snoopRespQueue),
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/gem5/tests/gem5/ |
H A D | suite.py | 86 _name = '{given_name}-{isa}-{opt}'.format( 91 _name += '-'+protocol 99 name=_name) 105 tests.append(verifier.instantiate_test(_name)) 120 name=_name,
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/gem5/src/arch/riscv/ |
H A D | faults.hh | 98 const FaultName _name; member in class:RiscvISA::RiscvFault 103 : _name(n), _interrupt(i), _code(c) 106 FaultName name() const override { return _name; } 118 const FaultName _name; member in class:RiscvISA::Reset 121 Reset() : _name("reset") {} 122 FaultName name() const override { return _name; }
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/gem5/src/systemc/tests/systemc/1666-2011-compliance/virtual_bind/ |
H A D | virtual_bind.cpp | 49 Chan(sc_module_name _name) argument 103 Child(sc_module_name _name) argument 124 Top(sc_module_name _name) argument
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/gem5/src/dev/ |
H A D | intel_8254_timer.hh | 110 std::string _name; member in class:Intel8254Timer::Counter 111 const std::string &name() const { return _name; } 197 std::string _name; member in class:Intel8254Timer 198 const std::string &name() const { return _name; }
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/gem5/src/systemc/tests/systemc/1666-2011-compliance/overkill_bug/ |
H A D | overkill_bug.cpp | 39 Top(sc_module_name _name) argument
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/gem5/src/systemc/tests/systemc/tmp/others/bogus_reset/ |
H A D | bogus_reset.cpp | 11 M5(sc_module_name _name)
argument
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/gem5/src/mem/ruby/system/ |
H A D | RubyPort.hh | 68 MemMasterPort(const std::string &_name, RubyPort *_port); 83 MemSlavePort(const std::string &_name, RubyPort *_port, 112 PioMasterPort(const std::string &_name, RubyPort *_port); 125 PioSlavePort(const std::string &_name, RubyPort *_port);
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/gem5/src/systemc/ |
H A D | tlm_port_wrapper.hh | 61 InitiatorSocket &i, const std::string &_name, PortID _id) : 62 Port(_name, _id), _initiator(i) 96 TlmTargetBaseWrapper(TargetSocket &t, const std::string &_name, argument 98 Port(_name, _id), _target(t) 60 TlmInitiatorBaseWrapper( InitiatorSocket &i, const std::string &_name, PortID _id) argument
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/gem5/src/cpu/simple/ |
H A D | atomic.hh | 119 AtomicCPUPort(const std::string &_name, BaseSimpleCPU* _cpu) argument 120 : MasterPort(_name, _cpu) 142 AtomicCPUDPort(const std::string &_name, BaseSimpleCPU* _cpu) argument 143 : AtomicCPUPort(_name, _cpu), cpu(_cpu)
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/gem5/src/dev/arm/ |
H A D | timer_a9global.hh | 87 std::string _name; member in class:A9GlobalTimer::Timer 129 std::string name() const { return _name; }
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