Searched refs:RegId (Results 26 - 48 of 48) sorted by relevance

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/gem5/src/cpu/minor/
H A Dscoreboard.hh111 bool findIndex(const RegId& reg, Index &scoreboard_index);
H A Ddyn_inst.hh232 RegId flatDestRegIdx[TheISA::MaxInstDestRegs];
H A Ddyn_inst.cc140 printRegName(std::ostream &os, const RegId& reg)
/gem5/src/cpu/
H A Dstatic_inst.hh216 const RegId& destRegIdx(int i) const { return _destRegIdx[i]; }
220 const RegId& srcRegIdx(int i) const { return _srcRegIdx[i]; }
234 RegId _destRegIdx[MaxInstDestRegs];
236 RegId _srcRegIdx[MaxInstSrcRegs];
H A Dthread_context.cc83 RegId rid(VecRegClass, i);
93 RegId rid(VecPredRegClass, i);
H A Dbase_dyn_inst.hh253 std::array<RegId, TheISA::MaxInstDestRegs> _flatDestRegIdx;
371 const RegId& flattenedDestRegIdx(int idx) const
409 void flattenDestReg(int idx, const RegId& flattened_dest)
606 const RegId& destRegIdx(int i) const { return staticInst->destRegIdx(i); }
609 const RegId& srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
/gem5/src/arch/arm/
H A Disa.hh448 RegId
449 flattenRegId(const RegId& regId) const
453 return RegId(IntRegClass, flattenIntIndex(regId.index()));
455 return RegId(FloatRegClass, flattenFloatIndex(regId.index()));
457 return RegId(VecRegClass, flattenVecIndex(regId.index()));
459 return RegId(VecElemClass, flattenVecElemIndex(regId.index()),
462 return RegId(VecPredRegClass,
465 return RegId(CCRegClass, flattenCCIndex(regId.index()));
467 return RegId(MiscRegClass, flattenMiscIndex(regId.index()));
469 return RegId();
[all...]
H A Dremote_gdb.cc214 auto v = (context->readVecReg(RegId(VecRegClass, i))).as<VecElem>();
243 RegId(VecRegClass, i))).as<VecElem>();
H A Dnativetrace.cc129 auto vec(tc->readVecReg(RegId(VecRegClass,i))
/gem5/src/arch/arm/tracers/
H A Dtarmac_record_v8.cc79 const RegId& reg)
163 RegId reg_id = staticInst->destRegIdx(reg);
H A Dtarmac_record_v8.hh98 TraceRegEntryV8(const TarmacContext& tarmCtx, const RegId& reg);
H A Dtarmac_record.cc153 const RegId& reg)
316 RegId reg_id = staticInst->destRegIdx(reg);
/gem5/src/arch/riscv/
H A Dutility.hh137 registerName(RegId reg)
/gem5/src/cpu/o3/
H A Ddyn_inst.hh176 const RegId& reg = si->srcRegIdx(idx);
187 const RegId& reg = si->destRegIdx(idx);
215 const RegId& original_dest_reg =
H A Drename.hh304 RenameHistory(InstSeqNum _instSeqNum, const RegId& _archReg,
315 RegId archReg;
H A Dthread_context_impl.hh338 RegId
339 O3ThreadContext<Impl>::flattenRegId(const RegId& regId) const
H A Dcpu.hh438 RegId(VecRegClass, reg_idx));
449 RegId(VecRegClass, reg_idx));
H A Drename_impl.hh1075 const RegId& src_reg = inst->srcRegIdx(src_idx);
1141 const RegId& dest_reg = inst->destRegIdx(dest_idx);
1144 RegId flat_dest_regid = tc->flattenRegId(dest_reg);
/gem5/src/arch/sparc/insts/
H A Dstatic_inst.cc64 SparcStaticInst::printRegArray(std::ostream &os, const RegId indexArray[],
97 SparcStaticInst::printReg(std::ostream &os, RegId reg)
/gem5/src/arch/arm/insts/
H A Dmisc.cc54 const RegId& reg = srcRegIdx(i);
82 const RegId& reg = destRegIdx(i);
/gem5/src/arch/x86/insts/
H A Dstatic_inst.cc123 X86StaticInst::printReg(std::ostream &os, RegId reg, int size) const
/gem5/src/cpu/checker/
H A Dcpu_impl.hh604 const RegId& idx = inst->destRegIdx(start_idx);
638 const RegId& idx = inst->destRegIdx(i);
/gem5/src/cpu/o3/probe/
H A Delastic_trace.cc247 const RegId& src_reg = dyn_inst->srcRegIdx(src_idx);
279 const RegId& dest_reg = dyn_inst->destRegIdx(dest_idx);

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