Searched refs:Mode (Results 26 - 45 of 45) sorted by relevance

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/gem5/src/gpu-compute/
H A Dshader.cc236 BaseTLB::Mode trans_mode;
384 Shader::functionalTLBAccess(PacketPtr pkt, int cu_id, BaseTLB::Mode mode)
H A Dgpu_tlb.cc702 Translation *translation, Mode mode,
905 Mode mode, int &latency)
915 Translation *translation, Mode mode, int &latency)
1126 TlbEntry * tlb_entry, Mode mode)
1170 Mode mode = sender_state->tlbMode;
1416 Mode mode = sender_state->tlbMode;
H A Dtlb_coalescer.cc120 // share a TLB Mode, i.e. they are both read
122 BaseTLB::Mode incoming_mode = incoming_state->tlbMode;
123 BaseTLB::Mode coalesced_mode = coalesced_state->tlbMode;
H A Dcompute_unit.cc756 BaseTLB::Mode TLB_mode;
1105 BaseTLB::Mode TLB_mode = translation_state->tlbMode;
/gem5/src/arch/alpha/
H A Dtlb.cc602 TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)
612 Translation *translation, Mode mode)
620 Mode mode) const
/gem5/src/arch/x86/
H A Dpagetable_walker.cc71 const RequestPtr &_req, BaseTLB::Mode _mode)
96 BaseTLB::Mode _mode)
181 BaseTLB::Mode _mode, bool _isTiming)
H A Dfaults.hh322 PageFault(Addr _addr, bool present, BaseTLB::Mode mode,
/gem5/src/cpu/o3/
H A Dfetch.hh131 BaseTLB::Mode mode)
H A Dlsq.hh732 ThreadContext* tc, BaseTLB::Mode mode);
804 ThreadContext* tc, BaseTLB::Mode mode);
H A Dlsq_impl.hh774 ThreadContext* tc, BaseTLB::Mode mode)
807 ThreadContext* tc, BaseTLB::Mode mode)
/gem5/src/cpu/simple/
H A Dtiming.hh128 BaseTLB::Mode mode)
H A Dtiming.cc430 BaseTLB::Mode mode = BaseTLB::Read;
508 BaseTLB::Mode mode = BaseTLB::Write;
576 BaseTLB::Mode mode = BaseTLB::Write;
/gem5/src/arch/arm/
H A Dtable_walker.hh783 BaseTLB::Mode mode;
908 bool _isHyp, TLB::Mode mode, TLB::Translation *_trans,
H A Disa.cc1663 BaseTLB::Mode mode = BaseTLB::Read;
1930 BaseTLB::Mode mode = BaseTLB::Read;
H A Dtable_walker.cc191 uint8_t _vmid, bool _isHyp, TLB::Mode _mode,
/gem5/src/arch/sparc/
H A Dtlb.cc837 TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)
847 Translation *translation, Mode mode)
855 ThreadContext *tc, Mode mode) const
/gem5/src/mem/cache/prefetch/
H A Dqueued.cc85 const RequestPtr &req, ThreadContext *tc, BaseTLB::Mode mode)
/gem5/src/cpu/minor/
H A Dfetch1.cc241 ThreadContext *tc, BaseTLB::Mode mode)
H A Dlsq.cc264 ThreadContext *tc, BaseTLB::Mode mode)
328 ThreadContext *tc, BaseTLB::Mode mode)
/gem5/src/cpu/kvm/
H A Dbase.cc1128 BaseTLB::Mode tlb_mode(write ? BaseTLB::Write : BaseTLB::Read);

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