/gem5/src/arch/arm/tracers/ |
H A D | tarmac_record_v8.cc | 65 uint8_t _size, Addr _addr, uint64_t _data)
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H A D | tarmac_record.hh | 168 uint8_t _size, Addr _addr, uint64_t _data);
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/gem5/src/gpu-compute/ |
H A D | GPU.py | 168 pio_addr = Param.Addr(0x200000000, "Device Address")
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/gem5/src/python/m5/ |
H A D | params.py | 722 class Addr(CheckedInt): class in inherits:CheckedInt 723 cxx_type = 'Addr' 727 if isinstance(value, Addr): 744 if isinstance(other, Addr): 769 self.end = Addr(kwargs.pop('end')) 771 self.end = self.start + Addr(kwargs.pop('size')) - 1 801 self.start = Addr(kwargs.pop('start')) 806 self.start = Addr(args[0]) 809 self.start = Addr(args[0][0]) 810 self.end = Addr(arg [all...] |
/gem5/src/mem/ |
H A D | port.hh | 122 void printAddr(Addr a);
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H A D | abstract_mem.cc | 213 Addr paddr = LockedAddr::mask(req->getPaddr()); 244 Addr paddr = LockedAddr::mask(req->getPaddr());
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/gem5/src/dev/arm/ |
H A D | gic_v3_redistributor.cc | 90 Gicv3Redistributor::read(Addr addr, size_t size, bool is_secure_access) 385 Gicv3Redistributor::write(Addr addr, uint64_t data, size_t size, 859 Addr lpi_pending_entry_ptr = lpiPendingTablePtr + (lpi_id / 8); 872 Addr lpi_pending_entry_ptr = lpiPendingTablePtr + (lpi_id / 8);
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H A D | ufs_device.cc | 1233 Addr address = 0x00; 1399 uint32_t req_pos, Addr finaladdress, uint32_t 1435 int req_pos, Addr finaladdress, uint32_t 1439 Addr cmd_desc_addr = 0x00; 1535 Addr finaladdress = UFSDevice[lun_id]->SCSIInfoQueue.front(). 1586 Addr response_addr = request_in->commandDescBaseAddrHi; 1627 Addr SCSI_start = sglist[count].upperAddr; 1706 UFSHostDevice::transferDone(Addr responseStartAddr, uint32_t req_pos, 1708 Addr address, uint8_t* destination, 1880 UFSHostDevice::writeDevice(Event* additional_action, bool toDisk, Addr [all...] |
H A D | gpu_nomali.cc | 152 const Addr addr(pkt->getAddr() - pioAddr); 173 const Addr addr(pkt->getAddr() - pioAddr);
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H A D | pl111.cc | 111 Addr daddr = pkt->getAddr() - pioAddr; 255 Addr daddr = pkt->getAddr() - pioAddr; 472 maxAddr = static_cast<Addr>(length * bytesPerPixel);
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/gem5/src/arch/x86/ |
H A D | interrupts.cc | 82 decodeAddr(Addr paddr) 193 Addr offset = pkt->getAddr() - pioAddr; 210 Addr offset = pkt->getAddr() - pioAddr; 309 Addr offset = pkt->getAddr() - x86InterruptAddress(initialApicId, 0);
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H A D | remote_gdb.cc | 72 RemoteGDB::acc(Addr va, size_t len) 83 Addr endVa = va + len - 1;
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/gem5/src/cpu/o3/ |
H A D | thread_context.hh | 363 Addr 370 Addr
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H A D | lsq_unit_impl.hh | 391 Addr invalidate_addr = pkt->getAddr() & cacheBlockMask; 454 Addr inst_eff_addr1 = inst->effAddr >> depCheckShift; 455 Addr inst_eff_addr2 = (inst->effAddr + inst->effSize - 1) >> depCheckShift; 469 Addr ld_eff_addr1 = ld_inst->effAddr >> depCheckShift; 470 Addr ld_eff_addr2 = 784 "to Addr:%#x, data:%#x [sn:%lli]\n",
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/gem5/src/mem/ruby/network/ |
H A D | MessageBuffer.cc | 326 MessageBuffer::reanalyzeMessages(Addr addr, Tick current_time) 364 MessageBuffer::stallMessage(Addr addr, Tick current_time)
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/gem5/configs/common/ |
H A D | FSConfig.py | 115 ranges = [AddrRange(IO_address_space_base, Addr.max)]) 165 self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'), 166 AddrRange(Addr('2GB'), size ='256MB')] 264 size_remain = long(Addr(mdesc.mem())) 470 Addr.max) 523 AddrRange(Addr('4GB'), size = excess_mem_size)]
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/gem5/src/dev/net/ |
H A D | i8254xGBe_defs.hh | 194 Addr buf; 202 Addr pkt; 203 Addr hdr; 245 inline Addr getBuf(TxDesc *d) { assert(isLegacy(d) || isData(d)); return d->d1; } 246 inline Addr getLen(TxDesc *d) { if (isLegacy(d)) return bits(d->d2,15,0); else return bits(d->d2, 19,0); }
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/gem5/src/arch/arm/insts/ |
H A D | static_inst.cc | 395 ArmStaticInst::printTarget(std::ostream &os, Addr target, 398 Addr symbolAddr; 479 const Addr addr, 482 Addr symbolAddr; 621 ArmStaticInst::generateDisassembly(Addr pc,
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H A D | macromem.cc | 1524 MicroIntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 1537 MicroIntImmXOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 1550 MicroSetPCCPSR::generateDisassembly(Addr pc, const SymbolTable *symtab) const 1559 MicroIntRegXOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 1571 MicroIntMov::generateDisassembly(Addr pc, const SymbolTable *symtab) const 1582 MicroIntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 1595 MicroMemOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 1612 MicroMemPairOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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/gem5/src/cpu/pred/ |
H A D | multiperspective_perceptron.cc | 544 MultiperspectivePerceptron::uncondBranch(ThreadID tid, Addr pc, 567 MultiperspectivePerceptron::lookup(ThreadID tid, Addr instPC, 609 MultiperspectivePerceptron::update(ThreadID tid, Addr instPC, bool taken, 612 Addr corrTarget) 810 MultiperspectivePerceptron::btbUpdate(ThreadID tid, Addr branch_pc,
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/gem5/src/arch/hsail/insts/ |
H A D | pseudo_inst.cc | 612 Addr addr = (((Addr) src_val1) << 32) | ((Addr) src_val2);
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/gem5/src/cpu/checker/ |
H A D | cpu_impl.hh | 239 Addr fetch_PC = thread->instAddr(); 307 Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset; 411 Addr oldpc;
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/gem5/src/arch/arm/ |
H A D | table_walker.cc | 456 Addr ttbr = 0; 512 Addr l1desc_addr = mbits(ttbr, 31, 14 - currState->ttbcr.n) | 557 Addr ttbr, ttbr0_max, ttbr1_min, desc_addr; 732 TableWalker::checkAddrSizeFaultAArch64(Addr addr, int currPhysAddrRange) 754 Addr ttbr = 0; 934 Addr base_addr = mbits(ttbr, 47, base_addr_lo); 976 Addr desc_addr = base_addr | 1517 Addr l2desc_addr; 1667 Addr next_desc_addr = currState->longDesc.nextDescAddr( 1976 TableWalker::fetchDescriptor(Addr descAdd [all...] |
/gem5/src/arch/mips/linux/ |
H A D | process.cc | 137 Addr bufPtr = process->getSyscallArg(tc, index); 166 Addr addr = process->getSyscallArg(tc, index);
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/gem5/src/arch/sparc/ |
H A D | process.cc | 58 Addr _StackBias) 373 Addr auxv_array_end = auxv_array_base;
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