Searched refs:Addr (Results 176 - 200 of 767) sorted by relevance

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/gem5/src/cpu/pred/
H A Dmultiperspective_perceptron_tage.hh66 void handleTAGEUpdate(Addr branch_pc, bool taken, TAGEBase::BranchInfo* bi)
72 int bindex(Addr pc_in) const override;
75 unsigned getUseAltIdx(TAGEBase::BranchInfo* bi, Addr branch_pc) override;
77 void updateHistories(ThreadID tid, Addr branch_pc, bool taken,
79 const StaticInstPtr &inst, Addr target) override;
82 bool taken, Addr branch_pc, Addr target);
124 void updateHistoryStack(Addr target, bool taken, bool is_call,
152 unsigned getIndBias(Addr branch_pc, StatisticalCorrector::BranchInfo* bi,
154 unsigned getIndBiasSK(Addr branch_p
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H A Dtage_sc_l_64KB.hh60 uint16_t gtag(ThreadID tid, Addr pc, int bank) const override;
66 Addr branch_pc, bool taken, TAGEBase::BranchInfo* bi) override;
113 unsigned getIndBiasBank(Addr branch_pc, BranchInfo* bi, int hitBank,
116 int gPredictions(ThreadID tid, Addr branch_pc, BranchInfo* bi,
121 void scHistoryUpdate(Addr branch_pc, const StaticInstPtr &inst, bool taken,
122 BranchInfo * tage_bi, Addr corrTarget) override;
124 void gUpdates(ThreadID tid, Addr pc, bool taken, BranchInfo* bi,
H A Dmultiperspective_perceptron_tage_64KB.hh65 int gPredictions(ThreadID tid, Addr branch_pc,
68 void getBiasLSUM(Addr branch_pc,
70 void gUpdates(ThreadID tid, Addr pc, bool taken,
72 void scHistoryUpdate(Addr branch_pc, const StaticInstPtr &inst, bool taken,
73 StatisticalCorrector::BranchInfo *bi, Addr corrTarget) override;
H A Dstatistical_corrector.hh94 int64_t getLocalHistory(int ordinal, Addr pc)
102 int ordinal, Addr branch_pc, bool taken, Addr extraXor = 0)
122 unsigned getEntry(Addr pc, unsigned idx)
218 ThreadID tid, Addr branch_pc, bool cond_branch, BranchInfo* bi,
223 virtual unsigned getIndBias(Addr branch_pc, BranchInfo* bi, bool b) const;
225 virtual unsigned getIndBiasSK(Addr branch_pc, BranchInfo* bi) const;
227 virtual unsigned getIndBiasBank( Addr branch_pc, BranchInfo* bi,
230 virtual unsigned getIndUpd(Addr branch_pc) const;
231 unsigned getIndUpds(Addr branch_p
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/gem5/src/dev/pci/
H A Ddevice.hh113 Addr BARAddrs[6];
123 isBAR(Addr addr, int bar) const
134 getBAR(Addr addr)
153 getBAR(Addr addr, int &bar, Addr &offs)
189 Addr pciToDma(Addr pci_addr) const {
H A DPciHost.py58 conf_base = Param.Addr("Config space base address")
59 conf_size = Param.Addr("Config space base address")
63 pci_pio_base = Param.Addr(0, "Base address for PCI IO accesses")
64 pci_mem_base = Param.Addr(0, "Base address for PCI memory accesses")
65 pci_dma_base = Param.Addr(0, "Base address for DMA memory accesses")
/gem5/src/arch/riscv/insts/
H A Damo.hh56 Addr pc, const SymbolTable *symtab) const override;
66 Addr pc, const SymbolTable *symtab) const override;
76 Addr pc, const SymbolTable *symtab) const override;
86 Addr pc, const SymbolTable *symtab) const override;
96 Addr pc, const SymbolTable *symtab) const override;
106 Addr pc, const SymbolTable *symtab) const override;
116 Addr pc, const SymbolTable *symtab) const override;
H A Damo.cc47 string MemFenceMicro::generateDisassembly(Addr pc,
62 string LoadReserved::generateDisassembly(Addr pc,
71 string LoadReservedMicro::generateDisassembly(Addr pc,
81 string StoreCond::generateDisassembly(Addr pc,
91 string StoreCondMicro::generateDisassembly(Addr pc,
102 string AtomicMemOp::generateDisassembly(Addr pc,
112 string AtomicMemOpMicro::generateDisassembly(Addr pc,
/gem5/src/arch/riscv/
H A Dlocked_mem.hh71 extern std::unordered_map<int, std::stack<Addr>> locked_addrs;
74 handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
76 std::stack<Addr>& locked_addr_stack = locked_addrs[xc->contextId()];
80 Addr snoop_addr = pkt->getAddr() & cacheBlockMask;
90 std::stack<Addr>& locked_addr_stack = locked_addrs[xc->contextId()];
102 handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask)
104 std::stack<Addr>& locked_addr_stack = locked_addrs[xc->contextId()];
/gem5/src/mem/
H A Dmulti_level_page_table.hh105 Addr
106 prepTopTable(System *system, Addr pageSize)
108 Addr addr = system->allocPhysPages(First::tableSize());
137 walk(System *system, Addr pageSize, Addr table, Addr vaddr,
148 walk(System *system, Addr pageSize, Addr table, Addr vaddr,
154 Addr nex
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/gem5/src/arch/sparc/
H A Dtlb.hh47 const Addr StartVAddrHole = ULL(0x0000800000000000);
48 const Addr EndVAddrHole = ULL(0xFFFF7FFFFFFFFFFF);
49 const Addr VAddrAMask = ULL(0xFFFFFFFF);
50 const Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF);
119 TlbEntry *lookup(Addr va, int partition_id, bool real, int context_id = 0,
127 void insert(Addr vpn, int partition_id, int context_id, bool real,
141 void demapPage(Addr va, int partition_id, bool real, int context_id);
144 bool validVirtualAddress(Addr va, bool am);
152 void writeTagAccess(Addr va, int context);
164 demapPage(Addr vadd
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/gem5/src/arch/sparc/insts/
H A Dbranch.cc47 Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
61 BranchImm13::generateDisassembly(Addr pc, const SymbolTable *symtab) const
78 BranchDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
82 Addr symbol_addr;
84 Addr target = disp + pc;
H A Dinteger.hh55 Addr pc, const SymbolTable *symtab) const override;
57 virtual bool printPseudoOps(std::ostream &os, Addr pc,
76 Addr pc, const SymbolTable *symtab) const override;
78 bool printPseudoOps(std::ostream &os, Addr pc,
128 Addr pc, const SymbolTable *symtab) const override;
/gem5/src/arch/alpha/
H A Dlocked_mem.hh69 handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
78 Addr locked_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask;
79 Addr snoop_addr = pkt->getAddr() & cacheBlockMask;
102 handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask)
111 Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR);
/gem5/src/arch/generic/
H A Dmmapped_ipr.cc44 const Addr offset(pkt->getAddr() & IPR_IN_CLASS_MASK);
58 Addr va(pkt->getAddr());
59 Addr cls(va >> IPR_CLASS_SHIFT);
75 Addr va(pkt->getAddr());
76 Addr cls(va >> IPR_CLASS_SHIFT);
H A Dmmapped_ipr.hh60 const Addr IPR_IN_CLASS_MASK = ULL(0x0000FFFFFFFFFFFF);
70 const Addr IPR_CLASS_PSEUDO_INST = 0x0;
83 inline Addr
/gem5/src/arch/mips/
H A Dlocked_mem.hh63 handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
68 Addr locked_addr = xc->readMiscReg(MISCREG_LLADDR) & cacheBlockMask;
69 Addr snoop_addr = pkt->getAddr() & cacheBlockMask;
95 handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask)
104 Addr lock_addr = xc->readMiscReg(MISCREG_LLADDR);
H A Dfaults.hh48 typedef Addr FaultVect;
193 Addr vaddr;
196 AddressFault(Addr _vaddr, bool _store) : vaddr(_vaddr), store(_store)
212 AddressErrorFault(Addr _vaddr, bool _store) :
228 Addr asid;
229 Addr vpn;
231 TlbFault(Addr _asid, Addr _vaddr, Addr _vpn, bool _store) :
258 Addr vec
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/gem5/src/arch/x86/
H A Dintmessage.hh77 static const Addr TriggerIntOffset = 0;
80 prepIntRequest(const uint8_t id, Addr offset, Addr size)
94 buildIntRequest(const uint8_t id, T payload, Addr offset, Addr size)
/gem5/src/dev/arm/
H A Damba_device.cc53 AmbaPioDevice::AmbaPioDevice(const Params *p, Addr pio_size)
58 AmbaIntDevice::AmbaIntDevice(const Params *p, Addr pio_size)
66 AmbaDmaDevice::AmbaDmaDevice(const Params *p, Addr pio_size)
74 AmbaDevice::readId(PacketPtr pkt, uint64_t amba_id, Addr pio_addr)
76 Addr daddr = pkt->getAddr() - pio_addr;
H A Dsmmu_v3_ptops.cc73 Addr
88 Addr
89 V7LPageTableOps::index(Addr va, unsigned level) const
102 Addr
113 Addr
166 Addr
182 Addr
183 V8PageTableOps4k::index(Addr va, unsigned level) const
194 Addr
206 Addr
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/gem5/src/mem/cache/tags/
H A Dsector_tags.hh129 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override;
147 CacheBlk* findBlock(Addr addr, bool is_secure) const override;
158 CacheBlk* findVictim(Addr addr, const bool is_secure,
168 int extractSectorOffset(Addr addr) const;
176 Addr regenerateBlkAddr(const CacheBlk* blk) const override;
/gem5/src/sim/
H A Dvptr.hh46 Addr ptr;
47 Addr buffer[(sizeof(T)-1)/sizeof(Addr) + 1];
50 explicit VPtr(ThreadContext *_tc, Addr p = 0)
98 operator=(Addr p)
/gem5/src/base/filters/
H A Dmulti_bit_sel_bloom_filter.cc58 MultiBitSel::set(Addr addr)
66 MultiBitSel::getCount(Addr addr) const
76 MultiBitSel::hash(Addr addr, int hash_number) const
78 uint64_t value = bits(addr, std::numeric_limits<Addr>::digits - 1,
80 const int max_bits = std::numeric_limits<Addr>::digits - offsetBits;
/gem5/src/mem/cache/prefetch/
H A Dbase.cc59 BasePrefetcher::PrefetchInfo::PrefetchInfo(PacketPtr pkt, Addr addr, bool miss)
70 Addr offset = pkt->req->getPaddr() - pkt->getAddr();
75 BasePrefetcher::PrefetchInfo::PrefetchInfo(PrefetchInfo const &pfi, Addr addr)
149 BasePrefetcher::inCache(Addr addr, bool is_secure) const
155 BasePrefetcher::inMissQueue(Addr addr, bool is_secure) const
161 BasePrefetcher::hasBeenPrefetched(Addr addr, bool is_secure) const
167 BasePrefetcher::samePage(Addr a, Addr b) const
172 Addr
173 BasePrefetcher::blockAddress(Addr
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