Searched hist:5558 (Results 1 - 9 of 9) sorted by relevance

/gem5/src/arch/mips/
H A Ddsp.cc5558:cb98f0fcc6c6 Fri Sep 26 11:18:00 EDT 2008 Nathan Binkert <nate@binkert.org> style: These files didn't even come close to following the M5 style guide.
H A Ddsp.hh5558:cb98f0fcc6c6 Fri Sep 26 11:18:00 EDT 2008 Nathan Binkert <nate@binkert.org> style: These files didn't even come close to following the M5 style guide.
/gem5/tests/configs/
H A Dtgen-simple-mem.py9788:5558ee8dd7d9 Thu Jun 27 05:49:00 EDT 2013 Akash Bagdia <akash.bagdia@arm.com> config: Remove redundant explicit setting of default clocks

This patch removes the explicit setting of the clock period for
certain instances of CoherentBus, NonCoherentBus and IOCache where the
specified clock is same as the default value of the system clock. As
all the values used are the defaults, there are no performance
changes. There are similar cases where the toL2Bus is set to use the
parent CPU clock which is already the default behaviour.

The main motivation for these simplifications is to ease the
introduction of clock domains.
H A Dbase_config.py9788:5558ee8dd7d9 Thu Jun 27 05:49:00 EDT 2013 Akash Bagdia <akash.bagdia@arm.com> config: Remove redundant explicit setting of default clocks

This patch removes the explicit setting of the clock period for
certain instances of CoherentBus, NonCoherentBus and IOCache where the
specified clock is same as the default value of the system clock. As
all the values used are the defaults, there are no performance
changes. There are similar cases where the toL2Bus is set to use the
parent CPU clock which is already the default behaviour.

The main motivation for these simplifications is to ease the
introduction of clock domains.
H A Dmemtest.py9788:5558ee8dd7d9 Thu Jun 27 05:49:00 EDT 2013 Akash Bagdia <akash.bagdia@arm.com> config: Remove redundant explicit setting of default clocks

This patch removes the explicit setting of the clock period for
certain instances of CoherentBus, NonCoherentBus and IOCache where the
specified clock is same as the default value of the system clock. As
all the values used are the defaults, there are no performance
changes. There are similar cases where the toL2Bus is set to use the
parent CPU clock which is already the default behaviour.

The main motivation for these simplifications is to ease the
introduction of clock domains.
/gem5/src/mem/ruby/system/
H A DRubySystem.py9788:5558ee8dd7d9 Thu Jun 27 05:49:00 EDT 2013 Akash Bagdia <akash.bagdia@arm.com> config: Remove redundant explicit setting of default clocks

This patch removes the explicit setting of the clock period for
certain instances of CoherentBus, NonCoherentBus and IOCache where the
specified clock is same as the default value of the system clock. As
all the values used are the defaults, there are no performance
changes. There are similar cases where the toL2Bus is set to use the
parent CPU clock which is already the default behaviour.

The main motivation for these simplifications is to ease the
introduction of clock domains.
/gem5/src/cpu/
H A DBaseCPU.py9788:5558ee8dd7d9 Thu Jun 27 05:49:00 EDT 2013 Akash Bagdia <akash.bagdia@arm.com> config: Remove redundant explicit setting of default clocks

This patch removes the explicit setting of the clock period for
certain instances of CoherentBus, NonCoherentBus and IOCache where the
specified clock is same as the default value of the system clock. As
all the values used are the defaults, there are no performance
changes. There are similar cases where the toL2Bus is set to use the
parent CPU clock which is already the default behaviour.

The main motivation for these simplifications is to ease the
introduction of clock domains.
/gem5/configs/example/
H A Dfs.py9788:5558ee8dd7d9 Thu Jun 27 05:49:00 EDT 2013 Akash Bagdia <akash.bagdia@arm.com> config: Remove redundant explicit setting of default clocks

This patch removes the explicit setting of the clock period for
certain instances of CoherentBus, NonCoherentBus and IOCache where the
specified clock is same as the default value of the system clock. As
all the values used are the defaults, there are no performance
changes. There are similar cases where the toL2Bus is set to use the
parent CPU clock which is already the default behaviour.

The main motivation for these simplifications is to ease the
introduction of clock domains.
/gem5/src/dev/arm/
H A DRealView.py9788:5558ee8dd7d9 Thu Jun 27 05:49:00 EDT 2013 Akash Bagdia <akash.bagdia@arm.com> config: Remove redundant explicit setting of default clocks

This patch removes the explicit setting of the clock period for
certain instances of CoherentBus, NonCoherentBus and IOCache where the
specified clock is same as the default value of the system clock. As
all the values used are the defaults, there are no performance
changes. There are similar cases where the toL2Bus is set to use the
parent CPU clock which is already the default behaviour.

The main motivation for these simplifications is to ease the
introduction of clock domains.

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