Searched hist:2011 (Results 651 - 675 of 897) sorted by relevance

<<21222324252627282930>>

/gem5/src/cpu/testers/rubytest/
H A DRubyTester.py8184:a8d64545cda6 Mon Mar 28 11:49:00 EDT 2011 Somayeh Sardashti <somayeh@cs.wisc.edu> This patch supports cache flushing in MOESI_hammer
/gem5/src/kern/linux/
H A Dprintk.cc8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
/gem5/src/mem/cache/prefetch/
H A Dbase.cc8533:8dac0abb7a1b Thu Sep 01 18:25:00 EDT 2011 Lisa Hsu <Lisa.Hsu@amd.com> Fix build for gcc-4.2 opt/fast

Even though the code is safe, compiler flags a warning here, which are treated as errors for fast/opt. I know it's redundant but it has no side effects and fixes the compile.
8509:afb40c3d4ba6 Fri Aug 19 16:08:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> Prefetcher: Fix some memory leaks with the prefetcher.
8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
/gem5/src/arch/arm/
H A Dsystem.hh8527:6bac5b04d588 Fri Aug 19 16:08:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Mark some variables uncacheable until boot all CPUs are enabled.

There are a set of locations is the linux kernel that are managed via
cache maintence instructions until all processors enable their MMUs & TLBs.
Writes to these locations are manually flushed from the cache to main
memory when the occur so that cores operating without their MMU enabled
and only issuing uncached accesses can receive the correct data. Unfortuantely,
gem5 doesn't support any kind of software directed maintence of the cache.
Until such time as that support exists this patch marks the specific cache blocks
that need to be coherent as non-cacheable until all CPUs enable their MMU and
thus allows gem5 to boot MP systems with caches enabled (a requirement for
booting an O3 cpu and thus an O3 CPU regression).
8286:abc8ab4ddd93 Wed May 04 21:38:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Add support for loading the a bootloader and configuring parameters for it
8285:c38905a6fa32 Wed May 04 21:38:00 EDT 2011 Prakash Ramrakhyani <Prakash.Ramrakhyani@arm.com> ARM: Implement WFE/WFI/SEV semantics.
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
/gem5/src/arch/x86/
H A Dpagetable_walker.cc8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
8096:021a0724c5c0 Sun Feb 27 19:24:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> X86: Use regular read requests in the walker instead of read exclusive.
7912:a9f05ab40763 Mon Feb 07 01:14:00 EST 2011 Joel Hestness <hestness@cs.utexas.edu> x86: Timing support for pagetable walker

Move page table walker state to its own object type, and make the
walker instantiate state for each outstanding walk. By storing the
states in a queue, the walker is able to handle multiple outstanding
timing requests. Note that functional walks use separate state
elements.
H A Dcpuid.cc7811:a8fc35183c10 Mon Jan 03 17:35:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Make commenting on close namespace brackets consistent.

Ran all the source files through 'perl -pi' with this script:

s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|;
s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|;
s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|;

Also did a little manual editing on some of the arch/*/isa_traits.hh files
and src/SConscript.
/gem5/src/cpu/o3/
H A Dlsq_unit_impl.hh8592:30a97c4198df Tue Sep 27 03:25:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> O3: Tidy up some DPRINTFs in the LSQ.
8591:8f23aeaf6a91 Tue Sep 27 03:24:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> Faults: Replace calls to genMachineCheckFault with M5PanicFault.
8587:acce52081b45 Mon Sep 26 01:18:00 EDT 2011 Nilay Vaish<nilay@cs.wisc.edu> LSQ: Moved a couple of lines to enable O3 + Ruby
This patch makes O3 CPU work along with the Ruby memory model. Ruby
overwrites the senderState pointer with another pointer. The pointer
is restored only when Ruby gets done with the packet. LSQ makes use of
senderState just after sendTiming() returns. But the dynamic_cast returns
a NULL pointer since Ruby's senderState pointer is from a different class.
Storing the senderState pointer before calling sendTiming() does away with
the problem.
8581:56f97760eadd Thu Sep 22 21:59:00 EDT 2011 Steve Reinhardt <steve.reinhardt@amd.com> event: minor cleanup
Initialize flags via the Event constructor instead of calling
setFlags() in the body of the derived class's constructor. I
forget exactly why, but this made life easier when implementing
multi-queue support.

Also rename Event::getFlags() to isFlagSet() to better match
common usage, and get rid of some unused Event methods.
8545:a3992291e230 Tue Sep 13 00:58:00 EDT 2011 Ali Saidi <saidi@eecs.umich.edu> LSQ: Only trigger a memory violation with a load/load if the value changes.

Only create a memory ordering violation when the value could have changed
between two subsequent loads, instead of just when loads go out-of-order
to the same address. While not very common in the case of Alpha, with
an architecture with a hardware table walker this can happen reasonably
frequently beacuse a translation will miss and start a table walk and
before the CPU re-schedules the faulting instruction another one will
pass it to the same address (or cache block depending on the dendency
checking).

This patch has been tested with a couple of self-checking hand crafted
programs to stress ordering between two cores.

The performance improvement on SPEC benchmarks can be substantial (2-10%).
8481:818aea9960f5 Sun Jul 31 22:21:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> O3: Implement memory mapped IPRs for O3.
8272:82057507f2f9 Wed May 04 21:38:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> O3: Fix a small corner case with the lsq hazard detection logic.
8247:acf4b902c02e Wed Apr 20 22:07:00 EDT 2011 Nathan Binkert <nate@binkert.org> stats: one more name violation
8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
H A Dthread_context.hh8777:dd43f1c9fa0a Mon Oct 31 05:58:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Make the functions available from the TC consistent between SE and FS.
8767:e575781f71b8 Sun Oct 30 03:33:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Make getProcessPtr available in both modes, and get rid of FULL_SYSTEMs.
8764:e4660687c49f Sun Oct 16 08:06:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Include getMemPort in FS.
8761:20322354b80b Sun Oct 16 08:06:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Build/expose vport in SE mode.
8754:0996451df6de Sun Oct 16 05:59:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> CPU: Make physPort and getPhysPort available in SE mode.
8541:27aaee8ec7cc Fri Sep 09 05:30:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> Decode: Pull instruction decoding out of the StaticInst class into its own.

This change pulls the instruction decoding machinery (including caches) out of
the StaticInst class and puts it into its own class. This has a few intrinsic
benefits. First, the StaticInst code, which has gotten to be quite large, gets
simpler. Second, the code that handles decode caching is now separated out
into its own component and can be looked at in isolation, making it easier to
understand. I took the opportunity to restructure the code a bit which will
hopefully also help.

Beyond that, this change also lays some ground work for each ISA to have its
own, potentially stateful decode object. We'd be able to include less
contextualizing information in the ExtMachInst objects since that context
would be applied at the decoder. Also, the decoder could "know" ahead of time
that all the instructions it's going to see are going to be, for instance, 64
bit mode, and it will have one less thing to check when it decodes them.
Because the decode caching mechanism has been separated out, it's now possible
to have multiple caches which correspond to different types of decoding
context. Having one cache for each element of the cross product of different
configurations may become prohibitive, so it may be desirable to clear out the
cache when relatively static state changes and not to have one for each
setting.

Because the decode function is no longer universally accessible as a static
member of the StaticInst class, a new function was added to the ThreadContexts
that returns the applicable decode object.
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
/gem5/src/mem/ruby/slicc_interface/
H A DAbstractController.hh8531:bfc59fbde824 Mon Aug 29 07:34:00 EDT 2011 Nilay Vaish<nilay@cs.wisc.edu> SLICC: Pass arguments by reference
Arguments to functions were being passed by value. This patch
changes SLICC so that arguments are passed by reference.
8436:5648986156db Thu Jun 30 20:49:00 EDT 2011 Brad Beckmann <Brad.Beckmann@amd.com>, Nilay Vaish <nilay@cs.wisc.edu> Ruby: Add support for functional accesses
This patch rpovides functional access support in Ruby. Currently only
the M5Port of RubyPort supports functional accesses. The support for
functional through the PioPort will be added as a separate patch.
8341:30daf1dd5c91 Wed Jun 08 12:58:00 EDT 2011 Nilay Vaish<nilay@cs.wisc.edu> Ruby: Correctly set access permissions for directory entries
The access permissions for the directory entries are not being set correctly.
This is because pointers are not used for handling directory entries.
function. get and set functions for access permissions have been added to the
Controller state machine. The changePermission() function provided by the
AbstractEntry and AbstractCacheEntry classes has been exposed to SLICC
code once again. The set_permission() functionality has been removed.

NOTE: Each protocol will have to define these get and set functions in order
to compile successfully.
8257:7226aebb77b4 Thu Apr 28 20:18:00 EDT 2011 Brad Beckmann <Brad.Beckmann@amd.com> network: convert links & switches to first class C++ SimObjects

This patch converts links and switches from second class simobjects that were
virtually ignored by the networks (both simple and Garnet) to first class
simobjects that directly correspond to c++ ojbects manipulated by the
topology and network classes. This is especially true for Garnet, where the
links and switches directly correspond to specific C++ objects.

By making this change, many aspects of the Topology class were simplified.
/gem5/src/base/
H A Dremote_gdb.cc8784:05fb20d7064b Wed Nov 02 05:11:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of FULL_SYSTEM in sim.
8783:8cd08c045cab Wed Nov 02 04:27:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get FULL_SYSTEM out of base/remote_gdb.cc.
8641:4d3ecac1abec Tue Dec 13 14:49:00 EST 2011 Nathan Binkert <nate@binkert.org> gcc: fix unused variable warnings from GCC 4.6.1
8332:23711432221f Thu Jun 02 17:36:00 EDT 2011 Nathan Binkert <nate@binkert.org> copyright: clean up copyright blocks
8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
7823:dac01f14f20f Sat Jan 08 00:50:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Replace curTick global variable with accessor functions.
This step makes it easy to replace the accessor functions
(which still access a global variable) with ones that access
per-thread curTick values.
/gem5/src/cpu/
H A Dsimple_thread.cc8793:5f25086326ac Fri Nov 18 04:33:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of FULL_SYSTEM in the CPU directory.
8777:dd43f1c9fa0a Mon Oct 31 05:58:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Make the functions available from the TC consistent between SE and FS.
8767:e575781f71b8 Sun Oct 30 03:33:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Make getProcessPtr available in both modes, and get rid of FULL_SYSTEMs.
8766:b0773af78423 Sun Oct 30 03:32:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Build the base process class in FS.
8761:20322354b80b Sun Oct 16 08:06:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Build/expose vport in SE mode.
8754:0996451df6de Sun Oct 16 05:59:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> CPU: Make physPort and getPhysPort available in SE mode.
7823:dac01f14f20f Sat Jan 08 00:50:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Replace curTick global variable with accessor functions.
This step makes it easy to replace the accessor functions
(which still access a global variable) with ones that access
per-thread curTick values.
H A Dsimple_thread.hh8794:e2ac2b7164dd Fri Nov 18 05:20:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of includes of config/full_system.hh.
8793:5f25086326ac Fri Nov 18 04:33:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of FULL_SYSTEM in the CPU directory.
8777:dd43f1c9fa0a Mon Oct 31 05:58:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Make the functions available from the TC consistent between SE and FS.
8761:20322354b80b Sun Oct 16 08:06:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Build/expose vport in SE mode.
8754:0996451df6de Sun Oct 16 05:59:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> CPU: Make physPort and getPhysPort available in SE mode.
8541:27aaee8ec7cc Fri Sep 09 05:30:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> Decode: Pull instruction decoding out of the StaticInst class into its own.

This change pulls the instruction decoding machinery (including caches) out of
the StaticInst class and puts it into its own class. This has a few intrinsic
benefits. First, the StaticInst code, which has gotten to be quite large, gets
simpler. Second, the code that handles decode caching is now separated out
into its own component and can be looked at in isolation, making it easier to
understand. I took the opportunity to restructure the code a bit which will
hopefully also help.

Beyond that, this change also lays some ground work for each ISA to have its
own, potentially stateful decode object. We'd be able to include less
contextualizing information in the ExtMachInst objects since that context
would be applied at the decoder. Also, the decoder could "know" ahead of time
that all the instructions it's going to see are going to be, for instance, 64
bit mode, and it will have one less thing to check when it decodes them.
Because the decode caching mechanism has been separated out, it's now possible
to have multiple caches which correspond to different types of decoding
context. Having one cache for each element of the cross product of different
configurations may become prohibitive, so it may be desirable to clear out the
cache when relatively static state changes and not to have one for each
setting.

Because the decode function is no longer universally accessible as a static
member of the StaticInst class, a new function was added to the ThreadContexts
that returns the applicable decode object.
8357:2fcd223a253b Sun Jun 19 21:43:00 EDT 2011 Korey Sewell <ksewell@umich.edu> simple-thread: give a name() function for debugging w/the SimpleThread object
8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
H A Dstatic_inst.hh8542:7230ff0738e3 Fri Sep 09 05:40:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> StaticInst: Merge StaticInst and StaticInstBase.

Having two StaticInst classes, one nominally ISA dependent and the other ISA
dependent, has not been historically useful and makes the StaticInst class
more complicated that it needs to be. This change merges StaticInstBase into
StaticInst.
8541:27aaee8ec7cc Fri Sep 09 05:30:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> Decode: Pull instruction decoding out of the StaticInst class into its own.

This change pulls the instruction decoding machinery (including caches) out of
the StaticInst class and puts it into its own class. This has a few intrinsic
benefits. First, the StaticInst code, which has gotten to be quite large, gets
simpler. Second, the code that handles decode caching is now separated out
into its own component and can be looked at in isolation, making it easier to
understand. I took the opportunity to restructure the code a bit which will
hopefully also help.

Beyond that, this change also lays some ground work for each ISA to have its
own, potentially stateful decode object. We'd be able to include less
contextualizing information in the ExtMachInst objects since that context
would be applied at the decoder. Also, the decoder could "know" ahead of time
that all the instructions it's going to see are going to be, for instance, 64
bit mode, and it will have one less thing to check when it decodes them.
Because the decode caching mechanism has been separated out, it's now possible
to have multiple caches which correspond to different types of decoding
context. Having one cache for each element of the cross product of different
configurations may become prohibitive, so it may be desirable to clear out the
cache when relatively static state changes and not to have one for each
setting.

Because the decode function is no longer universally accessible as a static
member of the StaticInst class, a new function was added to the ThreadContexts
that returns the applicable decode object.
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
8201:89221928d131 Mon Apr 04 12:42:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> CPU: Remove references to memory copy operations
8148:93982cb5044c Thu Mar 17 20:20:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Fix subtle bug in LDM.

If the instruction faults mid-op the base register shouldn't be written back.
7878:d3e6ebcccabf Fri Feb 04 00:47:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Fault: Rename sim/fault.hh to fault_fwd.hh to distinguish it from faults.hh.
/gem5/src/arch/sparc/
H A Dtlb.cc8751:a6c772fef2f1 Thu Oct 13 04:37:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SPARC: Remove the last checks of FULL_SYSTEM.
8748:01be402c5bf1 Mon Oct 10 03:31:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SPARC: Turn on handleIprRead and handleIprWrite in SE in SPARC.
8374:18173b099ed1 Sun Jun 19 21:43:00 EDT 2011 Korey Sewell <ksewell@umich.edu> sparc: init. cache state in TLB
valgrind complains and its a potential source of instability, so go ahead
and set it to 0 to start
8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
8105:906864dd0937 Wed Mar 02 02:18:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Spelling: Fix the a spelling error by changing mmaped to mmapped.

There may not be a formally correct spelling for the past tense of mmap, but
mmapped is the spelling Google doesn't try to autocorrect. This makes sense
because it mirrors the past tense of map->mapped and not the past tense of
cape->caped.
7811:a8fc35183c10 Mon Jan 03 17:35:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Make commenting on close namespace brackets consistent.

Ran all the source files through 'perl -pi' with this script:

s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|;
s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|;
s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|;

Also did a little manual editing on some of the arch/*/isa_traits.hh files
and src/SConscript.
/gem5/src/arch/
H A Disa_parser.py8588:ef28ed90449d Tue Sep 27 02:48:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ISA parser: Use '_' instead of '.' to delimit type modifiers on operands.

By using an underscore, the "." is still available and can unambiguously be
used to refer to members of a structure if an operand is a structure, class,
etc. This change mostly just replaces the appropriate "."s with "_"s, but
there were also a few places where the ISA descriptions where handling the
extensions themselves and had their own regular expressions to update. The
regular expressions in the isa parser were updated as well. It also now
looks for one of the defined type extensions specifically after connecting "_"
where before it would look for any sequence of characters after a "."
following an operand name and try to use it as the extension. This helps to
disambiguate cases where a "_" may legitimately be part of an operand name but
not separate the name from the type suffix.

Because leaving the "_" and suffix on the variable name still leaves a valid
C++ identifier and all extensions need to be consistent in a given context, I
considered leaving them on as a breadcrumb that would show what the intended
type was for that operand. Unfortunately the operands can be referred to in
code templates, the Mem operand in particular, and since the exact type of Mem
can be different for different uses of the same template, that broke things.
8538:b324639974f6 Thu Sep 08 06:21:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ISA parser: Don't look for operands in strings.
8537:00df5058a557 Thu Sep 08 06:20:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ISA parser: Match /* */ and // style comments.

Comments should not be scanned for operands, and we should look for both /* */
style and // style.
8465:9f3fedee88e2 Mon Jul 11 07:47:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ISA: Get rid of the unused mem_acc_type template parameter.
8452:3f2c329e9046 Tue Jul 05 21:30:00 EDT 2011 Nathan Binkert <nate@binkert.org> grammar: better encapsulation of a grammar and parsing
This makes it possible to use the grammar multiple times and use the multiple
instances concurrently. This makes implementing an include statement as part
of a grammar possible.
8449:4be49ad47c74 Tue Jul 05 19:52:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ISA parser: Define operand types with a ctype directly.
8448:86ed97566b23 Tue Jul 05 19:48:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ISA parser: Simplify operand type handling.

This change simplifies the code surrounding operand type handling and makes it
depend only on the ctype that goes with each operand type. Future changes will
allow defining operand types by their ctypes directly, convert the ISAs over
to that style of definition, and then remove support for the old style. These
changes are to make it easier to use non-builtin types like classes or
structures as the type for operands.
8339:1810956fa5dc Tue Jun 07 03:46:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ISA parser: Loosen the regular expressions matching filenames.

The regular expressions matching filenames in the ##include directives and the
internally generated ##newfile directives where only looking for filenames
composed of alpha numeric characters, periods, and dashes. In Unix/Linux, the
rules for what characters can be in a filename are much looser than that. This
change replaces those expressions with ones that look for anything other than
a quote character. Technically quote characters are allowed as well so we
should allow escaping them somehow, but the additional complexity probably
isn't worth it.
8176:46f5d6391f99 Thu Mar 24 13:55:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ISA parser: Set up op_src_decl and op_dest_decl for pc operands.
7816:b5003ac75977 Sat Jan 08 00:50:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> scons: show sources and targets when building, and colorize output.

I like the brevity of Ali's recent change, but the ambiguity of
sometimes showing the source and sometimes the target is a little
confusing. This patch makes scons typically list all sources and
all targets for each action, with the common path prefix factored
out for brevity. It's a little more verbose now but also more
informative.

Somehow Ali talked me into adding colors too, which is a whole
'nother story.
/gem5/src/dev/arm/
H A DRealView.py8742:9df38d259935 Tue Oct 04 05:26:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Put platform pointers in fewer objects.

Not all objects need a platform pointer, and having one creates a dependence
on their being a platform object. This change removes the platform pointer to
from the base device object and moves it into subclasses that actually need
it.
8525:5f3fe76e7950 Fri Aug 19 16:08:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Add VExpress_E support with PCIe to gem5
8524:1ddd1aa0e55b Fri Aug 19 16:08:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Add support for Versatile Express boards
8512:a508c2d92d63 Fri Aug 19 16:08:00 EDT 2011 Geoffrey Blake <geoffrey.blake@arm.com> ARM: Add per-cpu local timers for ARM.

Cortex-A9 processors can have a local timer and watchdog counter. It
is enabled by default in Linux and up to this point we've had to disable
them since a model wasn't available. This change allows a default
MP ARM Linux configuration to boot.
8461:7d0669201f80 Sun Jul 10 01:56:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> IO: Handle case where ISA Fake device is being used as a fake memory.
8299:64a938a8b7fc Fri May 13 18:27:00 EDT 2011 Chander Sudanthi <chander.sudanthi@arm.com> ARM: Better RealView/Versatile EB platform support.

Add registers and components to better support the VersatileEB board.
Made the MIDR and SYS_ID register parameters to ArmSystem and RealviewCtrl
respectively.
8283:ea5a46abdcca Wed May 04 21:38:00 EDT 2011 Prakash Ramrakhyani <Prakash.Ramrakhyani@arm.com> ARM: Make GIC handle IPIs and multiple processors.
8282:0cc4594abf28 Wed May 04 21:38:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Add snoop control unit device.
8212:134bd699967a Mon Apr 04 12:42:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Include IDE/CF controller by default in PBX model.

Frame buffer and boot linux:
./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxFrameBuf --kernel=vmlinux.touchkit
Linux from a CF card:
./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxCflash --kernel=vmlinux.touchkit
Run Android
./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmAndroid --kernel=vmlinux.android
Run MP
./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxCflash --kernel=vmlinux.mp-2.6.38
7950:1120b07dd4b0 Fri Feb 11 19:29:00 EST 2011 Ali Saidi <Ali.Saidi@ARM.com> VNC/ARM: Use VNC server and add support to boot into X11
/gem5/src/arch/alpha/isa/
H A Dmain.isa8738:66bf413b0d5b Fri Sep 30 03:27:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Use the new FullSystem constant where possible.
8588:ef28ed90449d Tue Sep 27 02:48:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ISA parser: Use '_' instead of '.' to delimit type modifiers on operands.

By using an underscore, the "." is still available and can unambiguously be
used to refer to members of a structure if an operand is a structure, class,
etc. This change mostly just replaces the appropriate "."s with "_"s, but
there were also a few places where the ISA descriptions where handling the
extensions themselves and had their own regular expressions to update. The
regular expressions in the isa parser were updated as well. It also now
looks for one of the defined type extensions specifically after connecting "_"
where before it would look for any sequence of characters after a "."
following an operand name and try to use it as the extension. This helps to
disambiguate cases where a "_" may legitimately be part of an operand name but
not separate the name from the type suffix.

Because leaving the "_" and suffix on the variable name still leaves a valid
C++ identifier and all extensions need to be consistent in a given context, I
considered leaving them on as a breadcrumb that would show what the intended
type was for that operand. Unfortunately the operands can be referred to in
code templates, the Mem operand in particular, and since the exact type of Mem
can be different for different uses of the same template, that broke things.
8449:4be49ad47c74 Tue Jul 05 19:52:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ISA parser: Define operand types with a ctype directly.
8442:b1f3dfae06f1 Sun Jul 03 01:34:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ISA: Use readBytes/writeBytes for all instruction level memory operations.
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
/gem5/src/cpu/checker/
H A Dthread_context.hh8793:5f25086326ac Fri Nov 18 04:33:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of FULL_SYSTEM in the CPU directory.
8767:e575781f71b8 Sun Oct 30 03:33:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Make getProcessPtr available in both modes, and get rid of FULL_SYSTEMs.
8764:e4660687c49f Sun Oct 16 08:06:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Include getMemPort in FS.
8761:20322354b80b Sun Oct 16 08:06:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Build/expose vport in SE mode.
8754:0996451df6de Sun Oct 16 05:59:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> CPU: Make physPort and getPhysPort available in SE mode.
/gem5/src/python/
H A DSConscript8597:45c9f664a365 Thu Oct 20 16:09:00 EDT 2011 Steve Reinhardt <steve.reinhardt@amd.com> SimObject: add export_method* hooks to export C++ methods to Python

Replace the (broken as of previous changeset) swig_objdecl() method
that allowed/forced you to substitute a whole new C++ struct
definition for SWIG to wrap with a set of export_method* hooks
that let you just declare a set of C++ methods (or other declarations)
that get inserted in the auto-generated struct.

Restore the System get/setMemoryMode methods, and use this mechanism
to specialize SimObject as well, eliminating teh need for sim_object.i.
Needed bits of sim_object.i are moved to the new pyobject.i.
Also sucked a little SimObject specialization into cxx_param_decl()
allowing us to get rid of src/sim/sim_object_params.hh. Now the
generation and wrapping of the base SimObject param struct is more
in line with how derived objects are handled.
8295:221013f9fd2f Thu May 12 14:19:00 EDT 2011 Nathan Binkert <nate@binkert.org> stats: better expose statistics to python.
Build a python list and dict of all stats and expose flags properly.
8224:75527411e636 Fri Apr 15 13:42:00 EDT 2011 Nathan Binkert <nate@binkert.org> region: add a utility class for keeping track of regions of some range

This is basically like the range_map stuff in src/base (range already
exists in Python). This code is like a set of ranges. I'm using it
to keep track of changed lines in source code, but it could be use to
keep track of memory ranges and holes in memory regions. It could
also be used in memory allocation type stuff. (Though it's not at all
optimized.)
8153:e641f702653a Fri Mar 18 14:47:00 EDT 2011 Steve Reinhardt <steve.reinhardt@amd.com> swig: get rid of m5.internal.random module (swig/random.i)
Thanks to swig this was interfering with the standard Python
random module. The only function in that module was seed(),
which erroneously called srand48(). Moved the function to
m5.internal.core, renamed it seedRandom(), and made it call
random_mt.init() instead.
7816:b5003ac75977 Sat Jan 08 00:50:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> scons: show sources and targets when building, and colorize output.

I like the brevity of Ali's recent change, but the ambiguity of
sometimes showing the source and sometimes the target is a little
confusing. This patch makes scons typically list all sources and
all targets for each action, with the common path prefix factored
out for brevity. It's a little more verbose now but also more
informative.

Somehow Ali talked me into adding colors too, which is a whole
'nother story.
/gem5/src/cpu/simple/
H A Dtiming.cc8793:5f25086326ac Fri Nov 18 04:33:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of FULL_SYSTEM in the CPU directory.
8779:2a590c51adb1 Tue Nov 01 07:01:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Expose the same methods on the CPUs in SE and FS modes.
8486:c4e77a9563f5 Sun Aug 07 12:21:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> Translation: Use a pointer type as the template argument.

This allows regular pointers and reference counted pointers without having to
use any shim structures or other tricks.
8444:56de1f9320df Sun Jul 03 01:35:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem.

readBytes and writeBytes had the word "bytes" in their names because they
accessed blobs of bytes. This distinguished them from the read and write
functions which handled higher level data types. Because those functions don't
exist any more, this change renames readBytes and writeBytes to more general
names, readMem and writeMem, which reflect the fact that they are how you read
and write memory. This also makes their names more consistent with the
register reading/writing functions, although those are still read and set for
some reason.
8443:530ff1bc8d70 Sun Jul 03 01:34:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ExecContext: Get rid of the now unused read/write templated functions.
8277:bfaab04cb292 Wed May 04 21:38:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> CPU: Add some useful debug message to the timing simple cpu.
8276:66bb0d8ae8bf Wed May 04 21:38:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> CPU: Fix a case where timing simple cpu faults can nest.

If we fault, change the state to faulting so that we don't fault again in the same cycle.
8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
8143:b0b94a7b7c1f Thu Mar 17 20:20:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Detect and skip udelay() functions in linux kernel.

This change speeds up booting, especially in MP cases, by not executing
udelay() on the core but instead skipping ahead tha amount of time that is being
delayed.
/gem5/
H A DSConstruct8614:2fc7787f47a9 Thu Nov 10 00:48:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> GCC: Guard some gcc flags so they're used when available and needed.
8492:1ad244a20877 Mon Aug 08 11:50:00 EDT 2011 Nilay Vaish<nilay@cs.wisc.edu> BuildEnv: Eliminate RUBY as build environment variable
This patch replaces RUBY with PROTOCOL in all the SConscript files as
the environment variable that decides whether or not certain components
of the simulator are compiled.
8483:b5052cad1fd3 Tue Aug 02 06:22:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> Scons: Make some Action objects fit the abreviated output format.
8482:353abb676fa2 Tue Aug 02 01:10:00 EDT 2011 Nilay Vaish<nilay@cs.wisc.edu> Scons: Drop RUBY as compile time option.
This patch drops RUBY as a compile time option. Instead the PROTOCOL option
is used to figure out whether or not to build Ruby. If the specified protocol
is 'None', then Ruby is not compiled.
8474:7f49e6a176b8 Tue Jul 19 05:56:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SCons: Only print all the SConsopts being read if verbose is turned on.
8336:3a2aebf01bf3 Fri Jun 03 00:23:00 EDT 2011 Steve Reinhardt <steve.reinhardt@amd.com> SConstruct: automatically update .hg/hgrc with style hooks.
Seems easier than pestering people about it.
Note also that path is now absolute, so you don't get errors
when invoking hg from subdirectories.
Also whacked unused mercurial_bin_not_found message (the
code that used this was deleted a couple months ago in
rev 5138d1e453f1).
8297:d57afdcf38f5 Thu May 12 14:19:00 EDT 2011 Nathan Binkert <nate@binkert.org> stats: delete mysql support
we can add it back within python in some future changeset
8268:3f49ed206f46 Mon May 02 03:40:00 EDT 2011 Steve Reinhardt <steve.reinhardt@amd.com> scons: interpret paths relative to launch directory

Make sure all command-line targets and EXTRAS directories
are interpreted relative to the launch directory. This
turns out to be very useful when building code from an
EXTRAS directory using SCons's -C option.

We were trying to do this with targets but it didn't actually
work since we didn't update BUILD_TARGETS (so SCons got
confused internally). We weren't even trying with EXTRAS.

To simplify the code, the default target is also interpreted
relative to the launch dir even though it was explicitly
handled as relative to the m5 dir before... I doubt anyone
really uses this anyway so it didn't seem worth the complexity.
(Maybe we should get rid of it?)
8267:06f3a4cbd585 Mon May 02 03:40:00 EDT 2011 Steve Reinhardt <steve.reinhardt@amd.com> scons: allow use of current builds as default build settings
Currently the --default= option only looks at the predefined
build configs (in m5/build_opts), so you're limited to basing
a new build config off of those (ALPHA_SE, etc.). If you've
already defined a non-standard build config and want to clone
it or tweak it, you have to start from scratch. This patch
causes --default= to look first among the existing builds
(in build/variables) before looking in build_opts so you
can specify an existing non-standard build config as a
starting point for a new config.
8152:a6052f50deed Fri Mar 18 14:47:00 EDT 2011 Steve Reinhardt <steve.reinhardt@amd.com> base: disable FastAlloc in debug builds by default
FastAlloc's reuse policies can mask allocation bugs, so
we typically want it disabled when debugging. Set
FORCE_FAST_ALLOC to enable even when debugging, and set
NO_FAST_ALLOC to disable even in non-debug builds.
/gem5/tests/configs/
H A Dsimple-atomic-mp.py8134:b01a51ff05fa Thu Mar 17 20:20:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> Mem: Fix issue with dirty block being lost when entire block transferred to non-cache.

This change fixes the problem for all the cases we actively use. If you want to try
more creative I/O device attachments (E.g. sharing an L2), this won't work. You
would need another level of caching between the I/O device and the cache
(which you actually need anyway with our current code to make sure writes
propagate). This is required so that you can mark the cache in between as
top level and it won't try to send ownership of a block to the I/O device.
Asserts have been added that should catch any issues.
7876:189b9b258779 Thu Feb 03 23:23:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Config: Keep track of uncached and cached ports separately.

This makes sure that the address ranges requested for caches and uncached ports
don't conflict with each other, and that accesses which are always uncached
(message signaled interrupts for instance) don't waste time passing through
caches.
H A Dsimple-timing-mp.py8134:b01a51ff05fa Thu Mar 17 20:20:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> Mem: Fix issue with dirty block being lost when entire block transferred to non-cache.

This change fixes the problem for all the cases we actively use. If you want to try
more creative I/O device attachments (E.g. sharing an L2), this won't work. You
would need another level of caching between the I/O device and the cache
(which you actually need anyway with our current code to make sure writes
propagate). This is required so that you can mark the cache in between as
top level and it won't try to send ownership of a block to the I/O device.
Asserts have been added that should catch any issues.
7876:189b9b258779 Thu Feb 03 23:23:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Config: Keep track of uncached and cached ports separately.

This makes sure that the address ranges requested for caches and uncached ports
don't conflict with each other, and that accesses which are always uncached
(message signaled interrupts for instance) don't waste time passing through
caches.
H A Dsimple-timing.py8134:b01a51ff05fa Thu Mar 17 20:20:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> Mem: Fix issue with dirty block being lost when entire block transferred to non-cache.

This change fixes the problem for all the cases we actively use. If you want to try
more creative I/O device attachments (E.g. sharing an L2), this won't work. You
would need another level of caching between the I/O device and the cache
(which you actually need anyway with our current code to make sure writes
propagate). This is required so that you can mark the cache in between as
top level and it won't try to send ownership of a block to the I/O device.
Asserts have been added that should catch any issues.
7876:189b9b258779 Thu Feb 03 23:23:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Config: Keep track of uncached and cached ports separately.

This makes sure that the address ranges requested for caches and uncached ports
don't conflict with each other, and that accesses which are always uncached
(message signaled interrupts for instance) don't waste time passing through
caches.
H A Dtsunami-simple-atomic-dual.py8134:b01a51ff05fa Thu Mar 17 20:20:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> Mem: Fix issue with dirty block being lost when entire block transferred to non-cache.

This change fixes the problem for all the cases we actively use. If you want to try
more creative I/O device attachments (E.g. sharing an L2), this won't work. You
would need another level of caching between the I/O device and the cache
(which you actually need anyway with our current code to make sure writes
propagate). This is required so that you can mark the cache in between as
top level and it won't try to send ownership of a block to the I/O device.
Asserts have been added that should catch any issues.
7876:189b9b258779 Thu Feb 03 23:23:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Config: Keep track of uncached and cached ports separately.

This makes sure that the address ranges requested for caches and uncached ports
don't conflict with each other, and that accesses which are always uncached
(message signaled interrupts for instance) don't waste time passing through
caches.

Completed in 408 milliseconds

<<21222324252627282930>>