Searched hist:2011 (Results 626 - 650 of 897) sorted by relevance

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/gem5/src/arch/mips/
H A Dremote_gdb.hh8544:2862c39f66f8 Sat Sep 10 06:45:00 EDT 2011 Deyuan Guo <guodeyuan@tsinghua.org.cn> MIPS: Implement gem5/src/arch/mips/remote_gdb.cc.
So a mips-cross-gdb can connect with gem5(MIPS_SE), and do some remote
debugging.

Testing:

Build gem5 for MIPS_SE and make gem5 wait at beginning:
modify "rgdb_wait = -1" to "rgdb_wait = 0" in src/sim/system.cc;
scons build/MIPS_SE/gem5.opt CPU_MODELS=O3CPU
----
Build GDB-7.3 mips-cross:
./configure --target=mips-linux-gnu --prefix=xxx/gdb-7.3-install/
make
make install
----
Run:
./build/MIPS_SE/gem5.opt configs/example/se.py --detailed --caches
./mips-linux-gnu-gdb xxx/gem5/tests/test-progs/hello/bin/mips/linux/hello
(gdb) target remote :7000
(gdb) info registers
(gdb) disassemble
(gdb) si
(gdb) break main
(gdb) c
(gdb) quit
Testing done.
H A Dstacktrace.cc8775:1e3ca5d77b53 Sun Oct 30 21:39:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of FULL_SYSTEM in MIPS.
/gem5/src/arch/alpha/
H A Dfaults.cc8780:89e0822462a1 Tue Nov 01 07:01:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of uses of FULL_SYSTEM in Alpha.
8539:7d3ea3c65c66 Fri Sep 09 04:01:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> Stack: Tidy up some comments, a warning, and make stack extension consistent.

Do some minor cleanup of some recently added comments, a warning, and change
other instances of stack extension to be like what's now being done for x86.
8405:cdf37bce69fc Sun Jun 19 21:43:00 EDT 2011 Korey Sewell <ksewell@umich.edu> alpha: naming for dtb faults
Just "dfault" gets confusing while debugging. Why not
differentiate whether it's an access violation or page
fault
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
H A DAlphaSystem.py8773:ac39e3421c34 Sun Oct 30 20:38:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> System: Push boot_cpu_frequency down into the subclasses that actually use it.

This parameter depends on a number of coincidences to work properly. First,
there must be an array assigned to system called "cpu" even though there's no
parameter called that. Second, the items in the "cpu" array have to have a
"clock" parameter which has a "frequency" member. This is true of the normal
CPUs, but isn't true of the memory tester CPUs. This happened to work before
because the memory tester CPUs were only used in SE mode where this parameter
was being excluded. Since everything is being pulled into a common binary,
this won't work any more. Since the boot_cpu_frequency parameter is only used
by Alpha's Linux System object (and Mips's through copy and paste), the
definition of that parameter is moved down to those objects specifically.
/gem5/util/m5/
H A Dm5op_x86.S7914:eee5bb0fb8ea Mon Feb 07 01:14:00 EST 2011 Brad Beckmann <Brad.Beckmann@amd.com> m5: added work completed monitoring support
H A DMakefile.arm8547:5979b029bbb4 Tue Sep 13 01:06:00 EDT 2011 Prakash Ramrakhyani <prakash.ramrakhyani@arm.com> gem5ops: Implement Java JNI for gem5Ops

These ops allow gem5 ops to be called from within java programs like the following:
import jni.gem5Op;

public class HelloWorld {

public static void main(String[] args) {
gem5Op gem5 = new gem5Op();
System.out.println("Rpns0:" + gem5.rpns());
System.out.println("Rpns1:" + gem5.rpns());
}

static {
System.loadLibrary("gem5OpJni");
}
}

When building you need to make sure classpath include gem5OpJni.jar:
javac -classpath $CLASSPATH:/path/to/gem5OpJni.jar HelloWorld.java

and when running you need to make sure both the java and library path are set:
java -classpath $CLASSPATH:/path/to/gem5OpJni.jar -Djava.library.path=/path/to/libgem5OpJni.so HelloWorld
/gem5/src/dev/arm/
H A Dtimer_cpulocal.cc8512:a508c2d92d63 Fri Aug 19 16:08:00 EDT 2011 Geoffrey Blake <geoffrey.blake@arm.com> ARM: Add per-cpu local timers for ARM.

Cortex-A9 processors can have a local timer and watchdog counter. It
is enabled by default in Linux and up to this point we've had to disable
them since a model wasn't available. This change allows a default
MP ARM Linux configuration to boot.
H A Dtimer_cpulocal.hh8512:a508c2d92d63 Fri Aug 19 16:08:00 EDT 2011 Geoffrey Blake <geoffrey.blake@arm.com> ARM: Add per-cpu local timers for ARM.

Cortex-A9 processors can have a local timer and watchdog counter. It
is enabled by default in Linux and up to this point we've had to disable
them since a model wasn't available. This change allows a default
MP ARM Linux configuration to boot.
/gem5/configs/common/
H A Dcpu2000.py8246:914389024c33 Wed Apr 20 22:07:00 EDT 2011 Nathan Binkert <nate@binkert.org> python: fix another bug from changes to main.py
H A DFSConfig.py8643:2f18d1ab589f Thu Dec 15 00:43:00 EST 2011 Anthony Gutierrez <atgutier@umich.edu> ARM: Update config files for Android/BBench images available on website.
8595:1f3c96b5d85e Wed Oct 19 19:08:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Fix small bug in config script that prevents android from booting
8528:1f95c9a0bb2f Fri Aug 19 16:08:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Add some MP regressions and clean up the disk images and kernels a bit
8525:5f3fe76e7950 Fri Aug 19 16:08:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Add VExpress_E support with PCIe to gem5
8524:1ddd1aa0e55b Fri Aug 19 16:08:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Add support for Versatile Express boards
8323:fd20dcf1a9aa Mon May 23 17:29:00 EDT 2011 Steve Reinhardt <steve.reinhardt@amd.com> config: revamp x86 config to avoid appending to SimObjectVectors
A significant contributor to the need for adoptOrphanParams()
is the practice of appending to SimObjectVectors which have
already been assigned as children. This practice sidesteps the
assignment operation for those appended SimObjects, which is
where parent/child relationships are typically established.

This patch reworks the config scripts that use append() on
SimObjectVectors, which all happen to be in the x86 system
configuration. At some point in the future, I hope to make
SimObjectVectors immutable (by deriving from tuple rather than
list), at which time this patch will be necessary for correct
operation. For now, it just avoids some of the warning
messages that get printed in adoptOrphanParams().
8287:45f3ac6b6a1c Wed May 04 21:38:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Configure bootloader parameters
8212:134bd699967a Mon Apr 04 12:42:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Include IDE/CF controller by default in PBX model.

Frame buffer and boot linux:
./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxFrameBuf --kernel=vmlinux.touchkit
Linux from a CF card:
./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxCflash --kernel=vmlinux.touchkit
Run Android
./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmAndroid --kernel=vmlinux.android
Run MP
./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxCflash --kernel=vmlinux.mp-2.6.38
8145:21e4f3a569fb Thu Mar 17 20:20:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Bare metal system should have 256MB of RAM.
8061:08e91664adac Wed Feb 23 16:10:00 EST 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Clarifies creation of Linux and baremetal ARM systems.

makeArmSystem creates both bare-metal and Linux systems more cleanly.
machine_type was never optional though listed as an optional argument; a system
such as "RealView_PBX" must now be explicitly specified. Now that it is a
required argument, the placement of the arguments has changed slightly
requiring some changes to calls that create ARM systems.
/gem5/src/arch/alpha/linux/
H A Dlinux.hh8600:b0d7c64ada19 Sun Oct 23 01:30:00 EDT 2011 Steve Reinhardt <steve.reinhardt@amd.com> syscall_emul: implement MAP_FIXED option to mmap()
/gem5/src/arch/power/
H A Dprocess.hh8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
/gem5/src/arch/sparc/linux/
H A Dlinux.hh8600:b0d7c64ada19 Sun Oct 23 01:30:00 EDT 2011 Steve Reinhardt <steve.reinhardt@amd.com> syscall_emul: implement MAP_FIXED option to mmap()
/gem5/src/cpu/o3/
H A Dinst_queue.hh8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
7944:1daf51f62013 Fri Feb 11 19:29:00 EST 2011 Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> O3: Enhance data address translation by supporting hardware page table walkers.

Some ISAs (like ARM) relies on hardware page table walkers. For those ISAs,
when a TLB miss occurs, initiateTranslation() can return with NoFault but with
the translation unfinished.

Instructions experiencing a delayed translation due to a hardware page table
walk are deferred until the translation completes and kept into the IQ. In
order to keep track of them, the IQ has been augmented with a queue of the
outstanding delayed memory instructions. When their translation completes,
instructions are re-executed (only their initiateAccess() was already
executed; their DTB translation is now skipped). The IEW stage has been
modified to support such a 2-pass execution.
7897:d9e8b1fd1a9f Mon Feb 07 01:14:00 EST 2011 Joel Hestness <hestness@cs.utexas.edu> mcpat: Adds McPAT performance counters

Updated patches from Rick Strong's set that modify performance counters for
McPAT
7813:7338bc628489 Mon Jan 03 17:35:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Move sched_list.hh and timebuf.hh from src/base to src/cpu.
These files really aren't general enough to belong in src/base.
This patch doesn't reorder include lines, leaving them unsorted
in many cases, but Nate's magic script will fix that up shortly.
H A Dmem_dep_unit_impl.hh8519:ef35ce2bd73f Fri Aug 19 16:08:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> LSQ: Set store predictor to periodically clear itself as recommended in the storesets paper.

This patch improves performance by as much as 10% on some spec benchmarks.
8516:a9c0d2ab490a Fri Aug 19 16:08:00 EDT 2011 Mrinmoy Ghosh <Mrinmoy.Ghosh@arm.com> LSQ: Add some better dprintfs for storeset predictor.
8515:12420b96b364 Fri Aug 19 16:08:00 EDT 2011 Mrinmoy Ghosh <Mrinmoy.Ghosh@arm.com> LSQ: Fix a few issues with the storeset predictor.

Two issues are fixed in this patch:
1. The load and store pc passed to the predictor are passed in reverse order.
2. The flag indicating that a barrier is inflight was never cleared when
the barrier was squashed instead of committed. This made all load insts
dependent on a non-existent barrier in-flight.
8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help
/gem5/src/cpu/simple/
H A DTimingSimpleCPU.py7876:189b9b258779 Thu Feb 03 23:23:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Config: Keep track of uncached and cached ports separately.

This makes sure that the address ranges requested for caches and uncached ports
don't conflict with each other, and that accesses which are always uncached
(message signaled interrupts for instance) don't waste time passing through
caches.
/gem5/src/mem/cache/prefetch/
H A Dtagged.cc8066:cb7bf3919bdd Wed Feb 23 16:10:00 EST 2011 Ali Saidi <Ali.Saidi@ARM.com> Includes: Don't include isa_traits.hh and use the TheISA namespace unless really needed.
/gem5/tests/configs/
H A Dt1000-simple-atomic.py7876:189b9b258779 Thu Feb 03 23:23:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Config: Keep track of uncached and cached ports separately.

This makes sure that the address ranges requested for caches and uncached ports
don't conflict with each other, and that accesses which are always uncached
(message signaled interrupts for instance) don't waste time passing through
caches.
/gem5/src/arch/arm/
H A Dprocess.cc8601:af28085882dc Sun Oct 23 01:30:00 EDT 2011 Steve Reinhardt <steve.reinhardt@amd.com> SE: move page allocation from PageTable to Process

PageTable supported an allocate() call that called back
through the Process to allocate memory, but did not have
a method to map addresses without allocating new pages.
It makes more sense for Process to do the allocation, so
this method was renamed allocateMem() and moved to Process,
and uses a new map() call on PageTable.

The remaining uses of the process pointer in PageTable
were only to get the name and the PID, so by passing these
in directly in the constructor, we can make PageTable
completely independent of Process.
8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help
8216:70e61aa65759 Sun Apr 10 21:02:00 EDT 2011 Ali Saidi <saidi@eecs.umich.edu> ARM: Fix checkpoint restoration in ARM_SE.
8177:a983c62ef6d0 Thu Mar 24 14:00:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> Arm: Get rid of the unused copyStringArray32 method from Arm process classes.
/gem5/src/arch/x86/linux/
H A Dsystem.cc8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
/gem5/src/arch/x86/
H A DX86TLB.py8752:28e899b7dee3 Thu Oct 13 05:22:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> X86: Turn on the page table walker in SE mode.
/gem5/src/cpu/pred/
H A D2bit_local.cc8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help
/gem5/src/kern/linux/
H A Dlinux.cc8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help
/gem5/src/cpu/testers/memtest/
H A Dmemtest.cc8436:5648986156db Thu Jun 30 20:49:00 EDT 2011 Brad Beckmann <Brad.Beckmann@amd.com>, Nilay Vaish <nilay@cs.wisc.edu> Ruby: Add support for functional accesses
This patch rpovides functional access support in Ruby. Currently only
the M5Port of RubyPort supports functional accesses. The support for
functional through the PioPort will be added as a separate patch.
8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
7823:dac01f14f20f Sat Jan 08 00:50:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Replace curTick global variable with accessor functions.
This step makes it easy to replace the accessor functions
(which still access a global variable) with ones that access
per-thread curTick values.
H A DMemTest.py8436:5648986156db Thu Jun 30 20:49:00 EDT 2011 Brad Beckmann <Brad.Beckmann@amd.com>, Nilay Vaish <nilay@cs.wisc.edu> Ruby: Add support for functional accesses
This patch rpovides functional access support in Ruby. Currently only
the M5Port of RubyPort supports functional accesses. The support for
functional through the PioPort will be added as a separate patch.

Completed in 171 milliseconds

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