Searched hist:12 (Results 1426 - 1450 of 2449) sorted by relevance
/gem5/src/systemc/ext/ | ||
H A D | systemc | 12852:300397457d0b Fri May 18 05:12:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Stub out all the standard utilility classes and functions. Change-Id: I9e9724edb6281e0b0a6bae5546b0ede77d295c12 Reviewed-on: https://gem5-review.googlesource.com/10841 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
/gem5/src/ | ||
H A D | Doxyfile | 9264:1607119c36bb Tue Sep 25 12:49:00 EDT 2012 Djordje Kovacevic <djordje.kovacevic@arm.com> MEM: Put memory system document into doxygen |
/gem5/src/arch/arm/isa/templates/ | ||
H A D | misc.isa | 8209:9e3f7f00fa90 Mon Apr 04 12:42:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Use CPU local lock before sending load to mem system. This change uses the locked_mem.hh header to handle implementing CLREX. It simplifies the current implementation greatly. 8205:7ecbffb674aa Mon Apr 04 12:42:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Cleanup implementation of ITSTATE and put important code in PCState. Consolidate all code to handle ITSTATE in the PCState object rather than touching a variety of structures/objects. 7612:917946898102 Mon Aug 23 12:18:00 EDT 2010 Gene Wu <Gene.Wu@arm.com> MEM: Make CLREX a first class request operation and clear locks in caches when it in received 7609:70e5fb74b4fa Mon Aug 23 12:18:00 EDT 2010 Gene Wu <Gene.Wu@arm.com> ARM: Implement CLREX init/complete acc methods |
/gem5/src/arch/generic/ | ||
H A D | mmapped_ipr.cc | 13234:dea0fbed3f19 Fri Oct 12 08:03:00 EDT 2018 Gabe Black <gabeblack@google.com> arch: Explicitly specify the endianness in the generic mem helpers. This avoids using the accessors which automatically assume an endianness, requiring the memory system to know what the guest ISA is. Change-Id: I863fa4116f00e77b801a2f8ea2fbe34e7f55fd5f Reviewed-on: https://gem5-review.googlesource.com/c/13461 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
/gem5/src/cpu/testers/directedtest/ | ||
H A D | DirectedGenerator.cc | 8832:247fee427324 Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> mem: Add a master ID to each request object. This change adds a master id to each request object which can be used identify every device in the system that is capable of issuing a request. This is part of the way to removing the numCpus+1 stats in the cache and replacing them with the master ids. This is one of a series of changes that make way for the stats output to be changed to python. |
/gem5/src/dev/arm/ | ||
H A D | gpu_nomali.cc | 13230:2988dc5d1d6f Fri Oct 12 07:58:00 EDT 2018 Gabe Black <gabeblack@google.com> arm: Use little endian packet accessors. We know data is little endian, so we can use those accessors explicitly. Change-Id: Iee337109fcda134e1ac5a700e5141fd7060f9c45 Reviewed-on: https://gem5-review.googlesource.com/c/13457 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
H A D | vio_mmio.cc | 13230:2988dc5d1d6f Fri Oct 12 07:58:00 EDT 2018 Gabe Black <gabeblack@google.com> arm: Use little endian packet accessors. We know data is little endian, so we can use those accessors explicitly. Change-Id: Iee337109fcda134e1ac5a700e5141fd7060f9c45 Reviewed-on: https://gem5-review.googlesource.com/c/13457 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
H A D | timer_sp804.cc | 13230:2988dc5d1d6f Fri Oct 12 07:58:00 EDT 2018 Gabe Black <gabeblack@google.com> arm: Use little endian packet accessors. We know data is little endian, so we can use those accessors explicitly. Change-Id: Iee337109fcda134e1ac5a700e5141fd7060f9c45 Reviewed-on: https://gem5-review.googlesource.com/c/13457 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> 12772:362544959c40 Mon Jun 04 12:50:00 EDT 2018 Nikos Nikoleris <nikos.nikoleris@arm.com> dev-arm: Fix the address range for some I/O devices Previously, many devices were incorrecty configured to respond to an address range of size 0xfff. This changes fixes this and sets it to 0x1000. Change-Id: I4b027a27adf60ceae4859e287d7f34443b398752 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11116 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> 7587:177151a54462 Mon Aug 23 12:18:00 EDT 2010 Ali Saidi <Ali.Saidi@arm.com> ARM: Change how the AMBA device ID checking is done to make it more generic 7584:28ddf6d9e982 Mon Aug 23 12:18:00 EDT 2010 Ali Saidi <Ali.Saidi@arm.com> ARM: Add I/O devices for booting linux |
H A D | pl011.hh | 11168:f98eb2da15a4 Mon Oct 12 04:07:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> misc: Remove redundant compiler-specific defines This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap (and similar) abstractions, as these are no longer needed with gcc 4.7 and clang 3.1 as minimum compiler versions. 9338:97b4a2be1e5b Fri Nov 02 12:32:00 EDT 2012 Andreas Sandberg <Andreas.Sandberg@arm.com> sim: Include object header files in SWIG interfaces When casting objects in the generated SWIG interfaces, SWIG uses classical C-style casts ( (Foo *)bar; ). In some cases, this can degenerate into the equivalent of a reinterpret_cast (mainly if only a forward declaration of the type is available). This usually works for most compilers, but it is known to break if multiple inheritance is used anywhere in the object hierarchy. This patch introduces the cxx_header attribute to Python SimObject definitions, which should be used to specify a header to include in the SWIG interface. The header should include the declaration of the wrapped object. We currently don't enforce header the use of the header attribute, but a warning will be generated for objects that do not use it. 7587:177151a54462 Mon Aug 23 12:18:00 EDT 2010 Ali Saidi <Ali.Saidi@arm.com> ARM: Change how the AMBA device ID checking is done to make it more generic 7584:28ddf6d9e982 Mon Aug 23 12:18:00 EDT 2010 Ali Saidi <Ali.Saidi@arm.com> ARM: Add I/O devices for booting linux |
/gem5/configs/common/ | ||
H A D | Benchmarks.py | 10697:71c40e5c8bd4 Fri Jan 16 15:12:00 EST 2015 Curtis Dunham <Curtis.Dunham@arm.com> config: add --root-device machine parameter In case /dev/sda1 is not actually the boot partition for an image, we can override it on the command line or in a benchmark definition. 8836:922edffe734d Sun Feb 12 18:18:00 EST 2012 Ali Saidi <saidi@eecs.umich.edu> configs: fix minor config bugs posted on the mailing list 8212:134bd699967a Mon Apr 04 12:42:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Include IDE/CF controller by default in PBX model. Frame buffer and boot linux: ./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxFrameBuf --kernel=vmlinux.touchkit Linux from a CF card: ./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxCflash --kernel=vmlinux.touchkit Run Android ./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmAndroid --kernel=vmlinux.android Run MP ./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxCflash --kernel=vmlinux.mp-2.6.38 2995:34553e4fd1ac Tue Aug 15 19:12:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> implement benchmark selection code |
/gem5/configs/example/arm/ | ||
H A D | fs_power.py | 11973:aa43e508ade4 Wed Apr 05 12:02:00 EDT 2017 Andreas Sandberg <andreas.sandberg@arm.com> config, arm: Add an example power model Add a script to demonstrate how power models can be wired to gem5 models. The script is meant as an example only and does not correlate with any realistic implementation. Change-Id: Ib95a74b2cb4af77a7816e3e8e89c89f3460775a1 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2721 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
/gem5/src/arch/arm/ | ||
H A D | ArmNativeTrace.py | 9338:97b4a2be1e5b Fri Nov 02 12:32:00 EDT 2012 Andreas Sandberg <Andreas.Sandberg@arm.com> sim: Include object header files in SWIG interfaces When casting objects in the generated SWIG interfaces, SWIG uses classical C-style casts ( (Foo *)bar; ). In some cases, this can degenerate into the equivalent of a reinterpret_cast (mainly if only a forward declaration of the type is available). This usually works for most compilers, but it is known to break if multiple inheritance is used anywhere in the object hierarchy. This patch introduces the cxx_header attribute to Python SimObject definitions, which should be used to specify a header to include in the SWIG interface. The header should include the declaration of the wrapped object. We currently don't enforce header the use of the header attribute, but a warning will be generated for objects that do not use it. |
/gem5/src/arch/x86/linux/ | ||
H A D | linux.hh | 8837:d492e0bb7e95 Sun Feb 12 19:41:00 EST 2012 Gabe Black <gblack@eecs.umich.edu> X86: open flags: Another patch from Vince Weaver 5976:536125d85fa3 Fri Feb 27 12:26:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Add a structure to allow mapping between the host and guest fstat formats. 5971:9c6391381323 Fri Feb 27 12:25:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Add a 32 bit mmap2 system call. 5960:c9c465241d3b Fri Feb 27 12:22:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Install some 32 bit system calls. |
/gem5/src/base/ | ||
H A D | circular_queue.test.cc | 13482:6af7a10675b4 Wed Apr 26 12:44:00 EDT 2017 Rekai Gonzalez-Alberquilla <rekai.gonzalezalberquilla@arm.com> base: Iterable CircularQueue implementation The former implementation of CircleBuf is functional but a bit too tailored to match a use-case. This patches introduces a new iterable circular queue, which adds some more functionality so it can also be used for the newer LSQ implementation, where iteration and iterators are a very desirable feature. Additional contributors: Gabor Dozsa. Change-Id: I5cfb95c8abc1f5e566a114acdbf23fc52a38ce5e Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13127 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> |
/gem5/src/cpu/ | ||
H A D | DummyChecker.py | 9340:40f8c6a8f38d Fri Nov 02 12:32:00 EDT 2012 Andreas Sandberg <Andreas.Sandberg@arm.com> cpu: Add header files for checker CPUs In order to create reliable SWIG wrappers, we need to include the declaration of the wrapped class in the SWIG file. Previously, we didn't expose the declaration of checker CPUs. This patch adds header files for such CPUs and include them in the SWIG wrapper. |
/gem5/src/dev/alpha/ | ||
H A D | AlphaBackdoor.py | 9338:97b4a2be1e5b Fri Nov 02 12:32:00 EDT 2012 Andreas Sandberg <Andreas.Sandberg@arm.com> sim: Include object header files in SWIG interfaces When casting objects in the generated SWIG interfaces, SWIG uses classical C-style casts ( (Foo *)bar; ). In some cases, this can degenerate into the equivalent of a reinterpret_cast (mainly if only a forward declaration of the type is available). This usually works for most compilers, but it is known to break if multiple inheritance is used anywhere in the object hierarchy. This patch introduces the cxx_header attribute to Python SimObject definitions, which should be used to specify a header to include in the SWIG interface. The header should include the declaration of the wrapped object. We currently don't enforce header the use of the header attribute, but a warning will be generated for objects that do not use it. |
/gem5/src/dev/ | ||
H A D | Platform.py | 9338:97b4a2be1e5b Fri Nov 02 12:32:00 EDT 2012 Andreas Sandberg <Andreas.Sandberg@arm.com> sim: Include object header files in SWIG interfaces When casting objects in the generated SWIG interfaces, SWIG uses classical C-style casts ( (Foo *)bar; ). In some cases, this can degenerate into the equivalent of a reinterpret_cast (mainly if only a forward declaration of the type is available). This usually works for most compilers, but it is known to break if multiple inheritance is used anywhere in the object hierarchy. This patch introduces the cxx_header attribute to Python SimObject definitions, which should be used to specify a header to include in the SWIG interface. The header should include the declaration of the wrapped object. We currently don't enforce header the use of the header attribute, but a warning will be generated for objects that do not use it. |
/gem5/src/dev/net/ | ||
H A D | etherbus.hh | 12130:5e0dd4d7b730 Wed Jun 28 12:18:00 EDT 2017 Sean Wilson <spwilson2@wisc.edu> net: Refactor some Event subclasses to lambdas Change-Id: I0e23f1529b26c36d749bf5211ee8623744d0b10f Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3927 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> |
/gem5/src/dev/serial/ | ||
H A D | Uart.py | 12689:f554325372e9 Mon Feb 26 12:27:00 EST 2018 Andreas Sandberg <andreas.sandberg@arm.com> dev: Add support for a simple debug UART Add a simple memory-mapped device that forwards writes to a serial devices and treats reads as reads from the device. Unlike real UART models, this one doesn't support interrupts. This is useful to implement various debug devices that exist in many systems. Change-Id: I1e4300e4d3b70825a15d03f47d4e026941f9066c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10025 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
/gem5/src/dev/x86/ | ||
H A D | PcSpeaker.py | 9338:97b4a2be1e5b Fri Nov 02 12:32:00 EDT 2012 Andreas Sandberg <Andreas.Sandberg@arm.com> sim: Include object header files in SWIG interfaces When casting objects in the generated SWIG interfaces, SWIG uses classical C-style casts ( (Foo *)bar; ). In some cases, this can degenerate into the equivalent of a reinterpret_cast (mainly if only a forward declaration of the type is available). This usually works for most compilers, but it is known to break if multiple inheritance is used anywhere in the object hierarchy. This patch introduces the cxx_header attribute to Python SimObject definitions, which should be used to specify a header to include in the SWIG interface. The header should include the declaration of the wrapped object. We currently don't enforce header the use of the header attribute, but a warning will be generated for objects that do not use it. |
H A D | I8237.py | 9338:97b4a2be1e5b Fri Nov 02 12:32:00 EDT 2012 Andreas Sandberg <Andreas.Sandberg@arm.com> sim: Include object header files in SWIG interfaces When casting objects in the generated SWIG interfaces, SWIG uses classical C-style casts ( (Foo *)bar; ). In some cases, this can degenerate into the equivalent of a reinterpret_cast (mainly if only a forward declaration of the type is available). This usually works for most compilers, but it is known to break if multiple inheritance is used anywhere in the object hierarchy. This patch introduces the cxx_header attribute to Python SimObject definitions, which should be used to specify a header to include in the SWIG interface. The header should include the declaration of the wrapped object. We currently don't enforce header the use of the header attribute, but a warning will be generated for objects that do not use it. |
/gem5/src/mem/probes/ | ||
H A D | MemTraceProbe.py | 11437:210624864179 Thu Apr 07 12:32:00 EDT 2016 Victor Garcia <victor.garcia@arm.com> mem: Add Program Counter to MemTraceProbe |
/gem5/src/mem/ruby/network/garnet2.0/ | ||
H A D | SwitchAllocator.cc | 11831:3c38d3e74980 Sun Feb 12 15:00:00 EST 2017 Tushar Krishna <tushar@ece.gatech.edu> ruby: fix round robin arbiter in garnet2.0 The rr arbiter pointer in garnet was getting updated on every request, even if there is no grant. This was leading to a huge variance in wait time at a router at high injection rates. This patch corrects it to update upon a grant. |
/gem5/src/mem/ruby/network/simple/ | ||
H A D | SimpleLink.py | 9338:97b4a2be1e5b Fri Nov 02 12:32:00 EDT 2012 Andreas Sandberg <Andreas.Sandberg@arm.com> sim: Include object header files in SWIG interfaces When casting objects in the generated SWIG interfaces, SWIG uses classical C-style casts ( (Foo *)bar; ). In some cases, this can degenerate into the equivalent of a reinterpret_cast (mainly if only a forward declaration of the type is available). This usually works for most compilers, but it is known to break if multiple inheritance is used anywhere in the object hierarchy. This patch introduces the cxx_header attribute to Python SimObject definitions, which should be used to specify a header to include in the SWIG interface. The header should include the declaration of the wrapped object. We currently don't enforce header the use of the header attribute, but a warning will be generated for objects that do not use it. |
/gem5/src/python/m5/ | ||
H A D | core.py | 5801:e0850da03cd4 Mon Jan 19 12:59:00 EST 2009 Nathan Binkert <nate@binkert.org> python: Try to isolate the stuff that's in the m5.internal package a bit more. |
Completed in 77 milliseconds