1// -*- mode:c++ -*- 2 3// Copyright (c) 2010-2013,2017-2018 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Redistribution and use in source and binary forms, with or without 16// modification, are permitted provided that the following conditions are 17// met: redistributions of source code must retain the above copyright 18// notice, this list of conditions and the following disclaimer; 19// redistributions in binary form must reproduce the above copyright 20// notice, this list of conditions and the following disclaimer in the 21// documentation and/or other materials provided with the distribution; 22// neither the name of the copyright holders nor the names of its 23// contributors may be used to endorse or promote products derived from 24// this software without specific prior written permission. 25// 26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37// 38// Authors: Gabe Black 39 40def template MrsDeclare {{ 41class %(class_name)s : public %(base_class)s 42{ 43 protected: 44 public: 45 // Constructor 46 %(class_name)s(ExtMachInst machInst, IntRegIndex _dest); 47 Fault execute(ExecContext *, Trace::InstRecord *) const override; 48}; 49}}; 50 51def template MrsConstructor {{ 52 %(class_name)s::%(class_name)s(ExtMachInst machInst, 53 IntRegIndex _dest) 54 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest) 55 { 56 %(constructor)s; 57 if (!(condCode == COND_AL || condCode == COND_UC)) { 58 for (int x = 0; x < _numDestRegs; x++) { 59 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 60 } 61 } 62 } 63}}; 64 65def template MrsBankedRegDeclare {{ 66class %(class_name)s : public %(base_class)s 67{ 68 protected: 69 uint8_t byteMask; 70 bool r; 71 72 public: 73 // Constructor 74 %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, 75 uint8_t _sysM, bool _r); 76 Fault execute(ExecContext *, Trace::InstRecord *) const override; 77}; 78}}; 79 80def template MrsBankedRegConstructor {{ 81 %(class_name)s::%(class_name)s(ExtMachInst machInst, 82 IntRegIndex _dest, 83 uint8_t _sysM, 84 bool _r) 85 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest), 86 byteMask(_sysM), r(_r) 87 { 88 %(constructor)s; 89 if (!(condCode == COND_AL || condCode == COND_UC)) { 90 for (int x = 0; x < _numDestRegs; x++) { 91 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 92 } 93 } 94 } 95}}; 96 97def template MsrBankedRegDeclare {{ 98class %(class_name)s : public %(base_class)s 99{ 100 protected: 101 bool r; 102 103 public: 104 // Constructor 105 %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, 106 uint8_t _sysM, bool _r); 107 Fault execute(ExecContext *, Trace::InstRecord *) const override; 108}; 109}}; 110 111def template MsrBankedRegConstructor {{ 112 %(class_name)s::%(class_name)s(ExtMachInst machInst, 113 IntRegIndex _op1, 114 uint8_t _sysM, 115 bool _r) 116 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, _sysM), 117 r(_r) 118 { 119 %(constructor)s; 120 if (!(condCode == COND_AL || condCode == COND_UC)) { 121 for (int x = 0; x < _numDestRegs; x++) { 122 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 123 } 124 } 125 } 126}}; 127 128def template MsrRegDeclare {{ 129class %(class_name)s : public %(base_class)s 130{ 131 protected: 132 public: 133 // Constructor 134 %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, uint8_t mask); 135 Fault execute(ExecContext *, Trace::InstRecord *) const override; 136}; 137}}; 138 139def template MsrRegConstructor {{ 140 %(class_name)s::%(class_name)s(ExtMachInst machInst, 141 IntRegIndex _op1, 142 uint8_t mask) 143 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, mask) 144 { 145 %(constructor)s; 146 if (!(condCode == COND_AL || condCode == COND_UC)) { 147 for (int x = 0; x < _numDestRegs; x++) { 148 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 149 } 150 } 151 } 152}}; 153 154def template MsrImmDeclare {{ 155class %(class_name)s : public %(base_class)s 156{ 157 protected: 158 public: 159 // Constructor 160 %(class_name)s(ExtMachInst machInst, uint32_t imm, uint8_t mask); 161 Fault execute(ExecContext *, Trace::InstRecord *) const override; 162}; 163}}; 164 165def template MsrImmConstructor {{ 166 %(class_name)s::%(class_name)s(ExtMachInst machInst, 167 uint32_t imm, 168 uint8_t mask) 169 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, imm, mask) 170 { 171 %(constructor)s; 172 if (!(condCode == COND_AL || condCode == COND_UC)) { 173 for (int x = 0; x < _numDestRegs; x++) { 174 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 175 } 176 } 177 } 178}}; 179 180def template MrrcOpDeclare {{ 181class %(class_name)s : public %(base_class)s 182{ 183 protected: 184 public: 185 // Constructor 186 %(class_name)s(ExtMachInst machInst, MiscRegIndex _op1, 187 IntRegIndex _dest, IntRegIndex _dest2, uint32_t imm); 188 Fault execute(ExecContext *, Trace::InstRecord *) const override; 189}; 190}}; 191 192def template MrrcOpConstructor {{ 193 %(class_name)s::%(class_name)s(ExtMachInst machInst, 194 MiscRegIndex op1, 195 IntRegIndex dest, 196 IntRegIndex dest2, 197 uint32_t imm) 198 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, op1, dest, 199 dest2, imm) 200 { 201 %(constructor)s; 202 if (!(condCode == COND_AL || condCode == COND_UC)) { 203 for (int x = 0; x < _numDestRegs; x++) { 204 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 205 } 206 } 207 } 208}}; 209 210def template McrrOpDeclare {{ 211class %(class_name)s : public %(base_class)s 212{ 213 protected: 214 public: 215 // Constructor 216 %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, IntRegIndex _op2, 217 MiscRegIndex _dest, uint32_t imm); 218 Fault execute(ExecContext *, Trace::InstRecord *) const override; 219}; 220}}; 221 222def template McrrOpConstructor {{ 223 %(class_name)s::%(class_name)s(ExtMachInst machInst, 224 IntRegIndex op1, 225 IntRegIndex op2, 226 MiscRegIndex dest, 227 uint32_t imm) 228 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, op1, op2, 229 dest, imm) 230 { 231 %(constructor)s; 232 if (!(condCode == COND_AL || condCode == COND_UC)) { 233 for (int x = 0; x < _numDestRegs; x++) { 234 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 235 } 236 } 237 } 238}}; 239 240def template ImmOpDeclare {{ 241class %(class_name)s : public %(base_class)s 242{ 243 protected: 244 public: 245 // Constructor 246 %(class_name)s(ExtMachInst machInst, uint64_t _imm); 247 Fault execute(ExecContext *, Trace::InstRecord *) const override; 248}; 249}}; 250 251def template ImmOpConstructor {{ 252 %(class_name)s::%(class_name)s(ExtMachInst machInst, uint64_t _imm) 253 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm) 254 { 255 %(constructor)s; 256 if (!(condCode == COND_AL || condCode == COND_UC)) { 257 for (int x = 0; x < _numDestRegs; x++) { 258 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 259 } 260 } 261 } 262}}; 263 264def template RegImmOpDeclare {{ 265class %(class_name)s : public %(base_class)s 266{ 267 protected: 268 public: 269 // Constructor 270 %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm); 271 Fault execute(ExecContext *, Trace::InstRecord *) const override; 272}; 273}}; 274 275def template RegImmOpConstructor {{ 276 %(class_name)s::%(class_name)s(ExtMachInst machInst, 277 IntRegIndex _dest, uint64_t _imm) 278 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm) 279 { 280 %(constructor)s; 281 if (!(condCode == COND_AL || condCode == COND_UC)) { 282 for (int x = 0; x < _numDestRegs; x++) { 283 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 284 } 285 } 286 } 287}}; 288 289def template RegRegOpDeclare {{ 290class %(class_name)s : public %(base_class)s 291{ 292 protected: 293 public: 294 // Constructor 295 %(class_name)s(ExtMachInst machInst, 296 IntRegIndex _dest, IntRegIndex _op1); 297 Fault execute(ExecContext *, Trace::InstRecord *) const override; 298}; 299}}; 300 301def template RegRegOpConstructor {{ 302 %(class_name)s::%(class_name)s(ExtMachInst machInst, 303 IntRegIndex _dest, IntRegIndex _op1) 304 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1) 305 { 306 %(constructor)s; 307 if (!(condCode == COND_AL || condCode == COND_UC)) { 308 for (int x = 0; x < _numDestRegs; x++) { 309 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 310 } 311 } 312 } 313}}; 314 315def template RegRegRegImmOpDeclare {{ 316class %(class_name)s : public %(base_class)s 317{ 318 protected: 319 public: 320 // Constructor 321 %(class_name)s(ExtMachInst machInst, 322 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, 323 uint64_t _imm); 324 Fault execute(ExecContext *, Trace::InstRecord *) const override; 325}; 326}}; 327 328def template RegRegRegImmOpConstructor {{ 329 %(class_name)s::%(class_name)s(ExtMachInst machInst, 330 IntRegIndex _dest, 331 IntRegIndex _op1, 332 IntRegIndex _op2, 333 uint64_t _imm) 334 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 335 _dest, _op1, _op2, _imm) 336 { 337 %(constructor)s; 338 if (!(condCode == COND_AL || condCode == COND_UC)) { 339 for (int x = 0; x < _numDestRegs; x++) { 340 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 341 } 342 } 343 } 344}}; 345 346def template RegRegRegRegOpDeclare {{ 347class %(class_name)s : public %(base_class)s 348{ 349 protected: 350 public: 351 // Constructor 352 %(class_name)s(ExtMachInst machInst, 353 IntRegIndex _dest, IntRegIndex _op1, 354 IntRegIndex _op2, IntRegIndex _op3); 355 Fault execute(ExecContext *, Trace::InstRecord *) const override; 356}; 357}}; 358 359def template RegRegRegRegOpConstructor {{ 360 %(class_name)s::%(class_name)s(ExtMachInst machInst, 361 IntRegIndex _dest, 362 IntRegIndex _op1, 363 IntRegIndex _op2, 364 IntRegIndex _op3) 365 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 366 _dest, _op1, _op2, _op3) 367 { 368 %(constructor)s; 369 if (!(condCode == COND_AL || condCode == COND_UC)) { 370 for (int x = 0; x < _numDestRegs; x++) { 371 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 372 } 373 } 374 } 375}}; 376 377def template RegRegRegOpDeclare {{ 378class %(class_name)s : public %(base_class)s 379{ 380 protected: 381 public: 382 // Constructor 383 %(class_name)s(ExtMachInst machInst, 384 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2); 385 Fault execute(ExecContext *, Trace::InstRecord *) const override; 386}; 387}}; 388 389def template RegRegRegOpConstructor {{ 390 %(class_name)s::%(class_name)s(ExtMachInst machInst, 391 IntRegIndex _dest, 392 IntRegIndex _op1, 393 IntRegIndex _op2) 394 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 395 _dest, _op1, _op2) 396 { 397 %(constructor)s; 398 if (!(condCode == COND_AL || condCode == COND_UC)) { 399 for (int x = 0; x < _numDestRegs; x++) { 400 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 401 } 402 } 403 } 404}}; 405 406def template RegRegImmOpDeclare {{ 407class %(class_name)s : public %(base_class)s 408{ 409 protected: 410 public: 411 // Constructor 412 %(class_name)s(ExtMachInst machInst, 413 IntRegIndex _dest, IntRegIndex _op1, 414 uint64_t _imm); 415 Fault execute(ExecContext *, Trace::InstRecord *) const override; 416}; 417}}; 418 419def template RegRegImmOpConstructor {{ 420 %(class_name)s::%(class_name)s(ExtMachInst machInst, 421 IntRegIndex _dest, 422 IntRegIndex _op1, 423 uint64_t _imm) 424 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 425 _dest, _op1, _imm) 426 { 427 %(constructor)s; 428 if (!(condCode == COND_AL || condCode == COND_UC)) { 429 for (int x = 0; x < _numDestRegs; x++) { 430 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 431 } 432 } 433 } 434}}; 435 436def template MiscRegRegImmOpDeclare {{ 437class %(class_name)s : public %(base_class)s 438{ 439 protected: 440 public: 441 // Constructor 442 %(class_name)s(ExtMachInst machInst, 443 MiscRegIndex _dest, IntRegIndex _op1, 444 uint64_t _imm); 445 Fault execute(ExecContext *, Trace::InstRecord *) const override; 446}; 447}}; 448 449def template MiscRegRegImmOpConstructor {{ 450 %(class_name)s::%(class_name)s(ExtMachInst machInst, 451 MiscRegIndex _dest, 452 IntRegIndex _op1, 453 uint64_t _imm) 454 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 455 _dest, _op1, _imm) 456 { 457 %(constructor)s; 458 if (!(condCode == COND_AL || condCode == COND_UC)) { 459 for (int x = 0; x < _numDestRegs; x++) { 460 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 461 } 462 } 463 } 464}}; 465 466def template RegMiscRegImmOpDeclare {{ 467class %(class_name)s : public %(base_class)s 468{ 469 protected: 470 public: 471 // Constructor 472 %(class_name)s(ExtMachInst machInst, 473 IntRegIndex _dest, MiscRegIndex _op1, 474 uint64_t _imm); 475 Fault execute(ExecContext *, Trace::InstRecord *) const override; 476}; 477}}; 478 479def template RegMiscRegImmOpConstructor {{ 480 %(class_name)s::%(class_name)s(ExtMachInst machInst, 481 IntRegIndex _dest, 482 MiscRegIndex _op1, 483 uint64_t _imm) 484 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 485 _dest, _op1, _imm) 486 { 487 %(constructor)s; 488 if (!(condCode == COND_AL || condCode == COND_UC)) { 489 for (int x = 0; x < _numDestRegs; x++) { 490 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 491 } 492 } 493 } 494}}; 495 496def template RegImmImmOpDeclare {{ 497class %(class_name)s : public %(base_class)s 498{ 499 protected: 500 public: 501 // Constructor 502 %(class_name)s(ExtMachInst machInst, 503 IntRegIndex _dest, uint64_t _imm1, uint64_t _imm2); 504 Fault execute(ExecContext *, Trace::InstRecord *) const override; 505}; 506}}; 507 508def template RegImmImmOpConstructor {{ 509 %(class_name)s::%(class_name)s(ExtMachInst machInst, 510 IntRegIndex _dest, 511 uint64_t _imm1, 512 uint64_t _imm2) 513 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 514 _dest, _imm1, _imm2) 515 { 516 %(constructor)s; 517 if (!(condCode == COND_AL || condCode == COND_UC)) { 518 for (int x = 0; x < _numDestRegs; x++) { 519 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 520 } 521 } 522 } 523}}; 524 525def template RegRegImmImmOpDeclare {{ 526class %(class_name)s : public %(base_class)s 527{ 528 protected: 529 public: 530 // Constructor 531 %(class_name)s(ExtMachInst machInst, 532 IntRegIndex _dest, IntRegIndex _op1, 533 uint64_t _imm1, uint64_t _imm2); 534 Fault execute(ExecContext *, Trace::InstRecord *) const override; 535}; 536}}; 537 538def template RegRegImmImmOpConstructor {{ 539 %(class_name)s::%(class_name)s(ExtMachInst machInst, 540 IntRegIndex _dest, 541 IntRegIndex _op1, 542 uint64_t _imm1, 543 uint64_t _imm2) 544 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 545 _dest, _op1, _imm1, _imm2) 546 { 547 %(constructor)s; 548 if (!(condCode == COND_AL || condCode == COND_UC)) { 549 for (int x = 0; x < _numDestRegs; x++) { 550 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 551 } 552 } 553 } 554}}; 555 556def template RegImmRegOpDeclare {{ 557class %(class_name)s : public %(base_class)s 558{ 559 protected: 560 public: 561 // Constructor 562 %(class_name)s(ExtMachInst machInst, 563 IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1); 564 Fault execute(ExecContext *, Trace::InstRecord *) const override; 565}; 566}}; 567 568def template RegImmRegOpConstructor {{ 569 %(class_name)s::%(class_name)s(ExtMachInst machInst, 570 IntRegIndex _dest, 571 uint64_t _imm, 572 IntRegIndex _op1) 573 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 574 _dest, _imm, _op1) 575 { 576 %(constructor)s; 577 if (!(condCode == COND_AL || condCode == COND_UC)) { 578 for (int x = 0; x < _numDestRegs; x++) { 579 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 580 } 581 } 582 } 583}}; 584 585def template RegImmRegShiftOpDeclare {{ 586class %(class_name)s : public %(base_class)s 587{ 588 protected: 589 public: 590 // Constructor 591 %(class_name)s(ExtMachInst machInst, 592 IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1, 593 int32_t _shiftAmt, ArmShiftType _shiftType); 594 Fault execute(ExecContext *, Trace::InstRecord *) const override; 595}; 596}}; 597 598def template RegImmRegShiftOpConstructor {{ 599 %(class_name)s::%(class_name)s(ExtMachInst machInst, 600 IntRegIndex _dest, 601 uint64_t _imm, 602 IntRegIndex _op1, 603 int32_t _shiftAmt, 604 ArmShiftType _shiftType) 605 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 606 _dest, _imm, _op1, _shiftAmt, _shiftType) 607 { 608 %(constructor)s; 609 if (!(condCode == COND_AL || condCode == COND_UC)) { 610 for (int x = 0; x < _numDestRegs; x++) { 611 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 612 } 613 } 614 } 615}}; 616 617def template MiscRegRegImmMemOpDeclare {{ 618 class %(class_name)s : public %(base_class)s 619 { 620 protected: 621 public: 622 // Constructor 623 %(class_name)s(ExtMachInst machInst, 624 MiscRegIndex _dest, IntRegIndex _op1, 625 uint64_t _imm); 626 Fault execute(ExecContext *, Trace::InstRecord *) const override; 627 Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; 628 Fault completeAcc(PacketPtr, ExecContext *, 629 Trace::InstRecord *) const override; 630 }; 631}}; 632 633def template Mcr15Execute {{ 634 Fault %(class_name)s::execute(ExecContext *xc, 635 Trace::InstRecord *traceData) const 636 { 637 Addr EA; 638 Fault fault = NoFault; 639 640 %(op_decl)s; 641 %(op_rd)s; 642 %(ea_code)s; 643 644 if (%(predicate_test)s) { 645 if (fault == NoFault) { 646 %(memacc_code)s; 647 } 648 649 if (fault == NoFault) { 650 Addr op_size = xc->tcBase()->getSystemPtr()->cacheLineSize(); 651 EA &= ~(op_size - 1); 652 fault = xc->writeMem(NULL, op_size, EA, memAccessFlags, NULL); 653 } 654 } else { 655 xc->setPredicate(false); 656 } 657 658 return fault; 659 } 660}}; 661 662def template Mcr15InitiateAcc {{ 663 Fault %(class_name)s::initiateAcc(ExecContext *xc, 664 Trace::InstRecord *traceData) const 665 { 666 Addr EA; 667 Fault fault = NoFault; 668 669 %(op_decl)s; 670 %(op_rd)s; 671 %(ea_code)s; 672 673 if (%(predicate_test)s) { 674 if (fault == NoFault) { 675 %(memacc_code)s; 676 } 677 678 if (fault == NoFault) { 679 Addr op_size = xc->tcBase()->getSystemPtr()->cacheLineSize(); 680 EA &= ~(op_size - 1); 681 fault = xc->writeMem(NULL, op_size, EA, memAccessFlags, NULL); 682 } 683 } else { 684 xc->setPredicate(false); 685 } 686 687 return fault; 688 } 689}}; 690 691def template Mcr15CompleteAcc {{ 692 Fault %(class_name)s::completeAcc(PacketPtr pkt, 693 ExecContext *xc, 694 Trace::InstRecord *traceData) const 695 { 696 return NoFault; 697 } 698}}; 699