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12616:4b463b4dc098 |
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23-Mar-2018 |
Gabe Black <gabeblack@google.com> |
arch: Fix all override related warnings.
Clang has started(?) reporting override related warnings, something gcc apparently did before, but was disabled in the SConstruct. Rather than disable the warnings in for clang as well, this change fixes the warnings. A future change will re-enable the warnings for gcc.
Change-Id: I3cc79e45749b2ae0f9bebb1acadc56a3d3a942da Reviewed-on: https://gem5-review.googlesource.com/9343 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
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12503:47b60911f9ba |
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19-Dec-2017 |
Nikos Nikoleris <nikos.nikoleris@arm.com> |
arch-arm: Fix cache line size for cache maintenace inst
Cache maintenance operations operate on whole cache blocks. This changeset uses the system cache line size as the size of the cache maintenance requests and masks the lower bits of the effective address.
Change-Id: I6e7aefff51670c8cac39e4e73db21a0c5a0b7aef Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7824 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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12358:386d26feb00f |
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07-Feb-2017 |
Nikos Nikoleris <nikos.nikoleris@arm.com> |
arm: Add support for the mcr dc{ic,i,c}mvac, dccmvau instructions
This patch adds support for the ARMv7 cache maintenance intructions: * mcr dccmvac cleans a VA to the PoC * mcr dcimvac invalidates a VA to the PoC * mcr dccimvac cleans and invalidates a VA to the PoC * mcr dccmvau cleans a VA to the PoU
Change-Id: I6511f203039ca145cc9128ddf61d09d6d7e40c10 Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5059 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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12236:126ac9da6050 |
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04-Nov-2017 |
Gabe Black <gabeblack@google.com> |
alpha,arm,mips,power,riscv,sparc,x86: Merge exec decl templates.
In the ISA instruction definitions, some classes were declared with execute, etc., functions outside of the main template because they had CPU specific signatures and would need to be duplicated with each CPU plugged into them. Now that the instructions always just use an ExecContext, there's no reason for those templates to be separate. This change folds those templates together.
Change-Id: I13bda247d3d1cc07c0ea06968e48aa5b4aace7fa Reviewed-on: https://gem5-review.googlesource.com/5401 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Alec Roelke <ar4jc@virginia.edu> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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10420:cc13df09fa55 |
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01-Oct-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
arm: More UBSan cleanups after additional full-system runs
Some incorrect casting to IntRegIndex, and a few uninitialized members in the i8254xGBe device.
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10418:7a76e13f0101 |
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27-Sep-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
arm: Fixed undefined behaviours identified by gcc
This patch fixes the runtime errors highlighted by the undefined behaviour sanitizer. In the end there were two issues. First, when rotating an immediate, we ended up shifting an uint32_t by 32 in some cases. This case is fixed by checking for a rotation by 0 positions. Second, the Mrc15 and Mcr15 are operating on an IntReg and a MiscReg, but we used the type RegRegImmOp and passed a MiscRegIndex as an IntRegIndex. This issue is resolved by introducing a MiscRegRegImmOp and RegMiscRegImmOp with the appropriate types.
With these fixes there are no runtime errors identified for the full ARM regressions.
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10184:bbfa3152bdea |
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09-May-2014 |
Curtis Dunham <Curtis.Dunham@arm.com> |
arch: remove inline specifiers on all inst constrs, all ISAs
With (upcoming) separate compilation, they are useless. Only link-time optimization could re-inline them, but ideally feedback-directed optimization would choose to do so only for profitable (i.e. common) instructions.
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10037:5cac77888310 |
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24-Jan-2014 |
ARM gem5 Developers |
arm: Add support for ARMv8 (AArch64 & AArch32)
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch.
Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch.
Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black
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8209:9e3f7f00fa90 |
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04-Apr-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Use CPU local lock before sending load to mem system.
This change uses the locked_mem.hh header to handle implementing CLREX. It simplifies the current implementation greatly.
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8205:7ecbffb674aa |
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04-Apr-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Cleanup implementation of ITSTATE and put important code in PCState.
Consolidate all code to handle ITSTATE in the PCState object rather than touching a variety of structures/objects.
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7848:cc5e64f8423f |
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18-Jan-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Add support for moving predicated false dest operands from sources.
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7712:7733c562e5e3 |
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22-Oct-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ISA: Simplify various implementations of completeAcc.
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7705:fd65f85fcc0c |
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13-Oct-2010 |
Gabe Black <gblack@eecs.umich.edu> |
Mem: Change the CLREX flag to CLEAR_LL.
CLREX is the name of an ARM instruction, not a name for this generic flag.
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7612:917946898102 |
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23-Aug-2010 |
Gene Wu <Gene.Wu@arm.com> |
MEM: Make CLREX a first class request operation and clear locks in caches when it in received
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7609:70e5fb74b4fa |
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23-Aug-2010 |
Gene Wu <Gene.Wu@arm.com> |
ARM: Implement CLREX init/complete acc methods
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7332:2e611548bb5a |
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02-Jun-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Add a new RegImmOp base class.
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7331:0897d3ccea91 |
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02-Jun-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Add a RegRegImmOp base class.
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7330:4f882b59745d |
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02-Jun-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Widen the immediate fields in the misc instruction classes.
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7306:548a5ee3dc5f |
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02-Jun-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Make a base class for instructions that use only an immediate.
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7261:5ed14bce7261 |
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02-Jun-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Rename the RevOp base class to something more generic.
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7253:38b991b82859 |
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02-Jun-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Add a register, immediate, immediate to register base for [su]bfx.
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7241:0a9f0db3e5d8 |
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02-Jun-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Add a base class to support usada8.
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7238:f68fa944baee |
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02-Jun-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Add a base class for the sel instruction.
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7233:687fa9b9c2b5 |
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02-Jun-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Add a base class for extend and add instructions.
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7232:f633e1a3f644 |
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02-Jun-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Generalize the saturation instruction bases for use in other instructions.
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7225:bf41a07cc7c0 |
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02-Jun-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Implement base classes for the saturation instructions.
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7208:589ddde61a77 |
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02-Jun-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Add base classes suitable for the REV* instructions.
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7202:b99579129992 |
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02-Jun-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Define versions of MSR and MRS outside the decoder.
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