1/*
2 * Copyright (c) 2010-2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 *          Andreas Sandberg
42 */
43
44
45/** @file
46 * Implementiation of a PL011 UART
47 */
48
49#ifndef __DEV_ARM_PL011_H__
50#define __DEV_ARM_PL011_H__
51
52#include "dev/arm/amba_device.hh"
53#include "dev/serial/uart.hh"
54
55class BaseGic;
56struct Pl011Params;
57
58class Pl011 : public Uart, public AmbaDevice
59{
60  public:
61    Pl011(const Pl011Params *p);
62
63    void serialize(CheckpointOut &cp) const override;
64    void unserialize(CheckpointIn &cp) override;
65
66  public: // PioDevice
67    Tick read(PacketPtr pkt) override;
68    Tick write(PacketPtr pkt) override;
69
70  public: // Uart
71    void dataAvailable() override;
72
73
74  protected: // Interrupt handling
75    /** Function to generate interrupt */
76    void generateInterrupt();
77
78    /**
79     * Assign new interrupt values and update interrupt signals
80     *
81     * A new interrupt is scheduled signalled if the set of unmasked
82     * interrupts goes empty to non-empty. Conversely, if the set of
83     * unmasked interrupts goes from non-empty to empty, the interrupt
84     * signal is cleared.
85     *
86     * @param ints New <i>raw</i> interrupt status
87     * @param mask New interrupt mask
88     */
89    void setInterrupts(uint16_t ints, uint16_t mask);
90    /**
91     * Convenience function to update the interrupt mask
92     *
93     * @see setInterrupts
94     * @param mask New interrupt mask
95     */
96    void setInterruptMask(uint16_t mask) { setInterrupts(rawInt, mask); }
97    /**
98     * Convenience function to raise a new interrupt
99     *
100     * @see setInterrupts
101     * @param ints Set of interrupts to raise
102     */
103    void raiseInterrupts(uint16_t ints) { setInterrupts(rawInt | ints, imsc); }
104    /**
105     * Convenience function to clear interrupts
106     *
107     * @see setInterrupts
108     * @param ints Set of interrupts to clear
109     */
110    void clearInterrupts(uint16_t ints) { setInterrupts(rawInt & ~ints, imsc); }
111
112    /** Masked interrupt status register */
113    inline uint16_t maskInt() const { return rawInt & imsc; }
114
115    /** Wrapper to create an event out of the thing */
116    EventFunctionWrapper intEvent;
117
118  protected: // Registers
119    static const uint64_t AMBA_ID = ULL(0xb105f00d00341011);
120    static const int UART_DR = 0x000;
121    static const int UART_RSR = 0x004;
122    static const int UART_ECR = 0x004;
123    static const int UART_FR = 0x018;
124    static const int UART_FR_CTS  = 0x001;
125    static const int UART_FR_RXFE = 0x010;
126    static const int UART_FR_TXFF = 0x020;
127    static const int UART_FR_RXFF = 0x040;
128    static const int UART_FR_TXFE = 0x080;
129    static const int UART_IBRD = 0x024;
130    static const int UART_FBRD = 0x028;
131    static const int UART_LCRH = 0x02C;
132    static const int UART_CR   = 0x030;
133    static const int UART_IFLS = 0x034;
134    static const int UART_IMSC = 0x038;
135    static const int UART_RIS  = 0x03C;
136    static const int UART_MIS  = 0x040;
137    static const int UART_ICR  = 0x044;
138    static const int UART_DMACR = 0x048;
139
140    static const uint16_t UART_RIINTR = 1 << 0;
141    static const uint16_t UART_CTSINTR = 1 << 1;
142    static const uint16_t UART_CDCINTR = 1 << 2;
143    static const uint16_t UART_DSRINTR = 1 << 3;
144    static const uint16_t UART_RXINTR = 1 << 4;
145    static const uint16_t UART_TXINTR = 1 << 5;
146    static const uint16_t UART_RTINTR = 1 << 6;
147    static const uint16_t UART_FEINTR = 1 << 7;
148    static const uint16_t UART_PEINTR = 1 << 8;
149    static const uint16_t UART_BEINTR = 1 << 9;
150    static const uint16_t UART_OEINTR = 1 << 10;
151
152    uint16_t control;
153
154    /** fractional baud rate divisor. Not used for anything but reporting
155     * written value */
156    uint16_t fbrd;
157
158    /** integer baud rate divisor. Not used for anything but reporting
159     * written value */
160    uint16_t ibrd;
161
162    /** Line control register. Not used for anything but reporting
163     * written value */
164    uint16_t lcrh;
165
166    /** interrupt fifo level register. Not used for anything but reporting
167     * written value */
168    uint16_t ifls;
169
170    /** interrupt mask register. */
171    uint16_t imsc;
172
173    /** raw interrupt status register */
174    uint16_t rawInt;
175
176  protected: // Configuration
177    /** Gic to use for interrupting */
178    BaseGic * const gic;
179
180    /** Should the simulation end on an EOT */
181    const bool endOnEOT;
182
183    /** Interrupt number to generate */
184    const int intNum;
185
186    /** Delay before interrupting */
187    const Tick intDelay;
188};
189
190#endif //__DEV_ARM_PL011_H__
191