| /gem5/src/cpu/o3/ |
| H A D | rename_impl.hh | 259 clearStates(ThreadID tid) argument
375 squash(const InstSeqNum &squash_seq_num, ThreadID tid) argument
446 ThreadID tid = *threads++; local
467 ThreadID tid = *threads++; local
493 rename(bool &status_change, ThreadID tid) argument
549 renameInsts(ThreadID tid) argument
803 skidInsert(ThreadID tid) argument
860 ThreadID tid = *threads++; local
879 ThreadID tid = *threads++; local
910 block(ThreadID tid) argument
944 unblock(ThreadID tid) argument
965 doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid) argument
1015 removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid) argument
1066 renameSrcRegs(const DynInstPtr &inst, ThreadID tid) argument
1133 renameDestRegs(const DynInstPtr &inst, ThreadID tid) argument
1187 calcFreeROBEntries(ThreadID tid) argument
1199 calcFreeIQEntries(ThreadID tid) argument
1211 calcFreeLQEntries(ThreadID tid) argument
1225 calcFreeSQEntries(ThreadID tid) argument
1251 readStallSignals(ThreadID tid) argument
1265 checkStall(ThreadID tid) argument
1297 readFreeEntries(ThreadID tid) argument
1333 checkSignalsAndUpdate(ThreadID tid) argument
1433 serializeAfter(InstQueue &inst_list, ThreadID tid) argument
[all...] |
| H A D | fetch_impl.hh | 334 DefaultFetch<Impl>::clearStates(ThreadID tid) argument
391 ThreadID tid = cpu->contextToThread(pkt->req->contextId()); local
501 drainStall(ThreadID tid) argument
547 deactivateThread(ThreadID tid) argument
573 ThreadID tid = inst->threadNumber; local
604 fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc) argument
657 ThreadID tid = cpu->contextToThread(mem_req->contextId()); local
761 doSquash(const TheISA::PCState &newPC, const DynInstPtr squashInst, ThreadID tid) argument
813 squashFromDecode(const TheISA::PCState &newPC, const DynInstPtr squashInst, const InstSeqNum seq_num, ThreadID tid) argument
850 ThreadID tid = *threads++; local
883 squash(const TheISA::PCState &newPC, const InstSeqNum seq_num, DynInstPtr squashInst, ThreadID tid) argument
910 ThreadID tid = *threads++; local
967 ThreadID tid = *tid_itr; local
999 checkSignalsAndUpdate(ThreadID tid) argument
1104 buildInst(ThreadID tid, StaticInstPtr staticInst, StaticInstPtr curMacroop, TheISA::PCState thisPC, TheISA::PCState nextPC, bool trace) argument
1473 ThreadID tid = *thread; local
1529 ThreadID tid = *threads++; local
1566 ThreadID tid = *threads++; local
1599 pipelineIcacheAccesses(ThreadID tid) argument
1629 profileStall(ThreadID tid) argument
[all...] |
| H A D | inst_queue_impl.hh | 511 ThreadID tid = *threads++; local
532 numFreeEntries(ThreadID tid) argument
552 isFull(ThreadID tid) argument
841 ThreadID tid = issuing_inst->threadNumber; local
953 ThreadID tid = (*inst_it).second->threadNumber; local
972 commit(const InstSeqNum &inst, ThreadID tid) argument
1131 ThreadID tid = completed_inst->threadNumber; local
1208 squash(ThreadID tid) argument
1225 doSquash(ThreadID tid) argument
[all...] |
| H A D | cpu.cc | 633 activateThread(ThreadID tid) argument
651 deactivateThread(ThreadID tid) argument
698 activateContext(ThreadID tid) argument
737 suspendContext(ThreadID tid) argument
758 haltContext(ThreadID tid) argument
772 insertThread(ThreadID tid) argument
824 removeThread(ThreadID tid) argument
868 switchRenameMode(ThreadID tid, UnifiedFreeList* freelist) argument
912 trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst) argument
921 syscall(int64_t callnum, ThreadID tid, Fault *fault) argument
948 unserializeThread(CheckpointIn &cp, ThreadID tid) argument
1085 commitDrained(ThreadID tid) argument
1176 readMiscReg(int misc_reg, ThreadID tid) argument
1184 setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid) argument
1191 setMiscReg(int misc_reg, RegVal val, ThreadID tid) argument
1316 readArchIntReg(int reg_idx, ThreadID tid) argument
1327 readArchFloatReg(int reg_idx, ThreadID tid) argument
1388 readArchCCReg(int reg_idx, ThreadID tid) argument
1399 setArchIntReg(int reg_idx, RegVal val, ThreadID tid) argument
1410 setArchFloatReg(int reg_idx, RegVal val, ThreadID tid) argument
1421 setArchVecReg(int reg_idx, const VecRegContainer& val, ThreadID tid) argument
1431 setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx, const VecElem& val, ThreadID tid) argument
1441 setArchVecPredReg(int reg_idx, const VecPredRegContainer& val, ThreadID tid) argument
1451 setArchCCReg(int reg_idx, RegVal val, ThreadID tid) argument
1462 pcState(ThreadID tid) argument
1469 pcState(const TheISA::PCState &val, ThreadID tid) argument
1476 instAddr(ThreadID tid) argument
1483 nextInstAddr(ThreadID tid) argument
1490 microPC(ThreadID tid) argument
1497 squashFromTC(ThreadID tid) argument
1514 instDone(ThreadID tid, const DynInstPtr &inst) argument
1550 removeInstsNotInROB(ThreadID tid) argument
1595 removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid) argument
1624 squashInstIt(const ListIt &instIt, ThreadID tid) argument
1721 wakeup(ThreadID tid) argument
1765 addThreadToExitingList(ThreadID tid) argument
1792 scheduleThreadExitEvent(ThreadID tid) argument
[all...] |
| H A D | cpu.hh | 446 setArchVecLane(int reg_idx, int lId, ThreadID tid, const LD& val) argument
678 tcBase(ThreadID tid) argument
[all...] |
| H A D | lsq.hh | 858 void commitLoads(InstSeqNum &youngest_inst, ThreadID tid) argument
864 void commitStores(InstSeqNum &youngest_inst, ThreadID tid) argument
879 squash(const InstSeqNum &squashed_num, ThreadID tid) argument
890 bool violation(ThreadID tid) { return thread.at(tid).violation(); } argument
894 getMemDepViolator(ThreadID tid) argument
900 getLoadHead(ThreadID tid) argument
904 getLoadHeadSeqNum(ThreadID tid) argument
910 getStoreHead(ThreadID tid) argument
914 getStoreHeadSeqNum(ThreadID tid) argument
922 getCount(ThreadID tid) argument
927 numLoads(ThreadID tid) argument
932 numStores(ThreadID tid) argument
991 hasStoresToWB(ThreadID tid) argument
994 numStoresToWB(ThreadID tid) argument
1001 willWB(ThreadID tid) argument
1123 ThreadID tid = cpu->contextToThread(req->request()->contextId()); local
1132 ThreadID tid = cpu->contextToThread(req->request()->contextId()); local
[all...] |
| /gem5/src/cpu/pred/ |
| H A D | multiperspective_perceptron.cc | 246 MultiperspectivePerceptron::findBest(ThreadID tid, argument
272 MultiperspectivePerceptron::getIndex(ThreadID tid, const MPPBranchInfo &bi, argument
303 MultiperspectivePerceptron::computeOutput(ThreadID tid, MPPBranchInfo &bi) argument
403 train(ThreadID tid, MPPBranchInfo &bi, bool taken) argument
544 uncondBranch(ThreadID tid, Addr pc, void * &bp_history) argument
567 lookup(ThreadID tid, Addr instPC, void * &bp_history) argument
609 update(ThreadID tid, Addr instPC, bool taken, void *bp_history, bool squashed, const StaticInstPtr & inst, Addr corrTarget) argument
810 btbUpdate(ThreadID tid, Addr branch_pc, void* &bp_history) argument
816 squash(ThreadID tid, void *bp_history) argument
[all...] |
| H A D | multiperspective_perceptron_tage.cc | 348 MPP_StatisticalCorrector::scPredict(ThreadID tid, Addr branch_pc, argument
411 MultiperspectivePerceptronTAGE::getIndex(ThreadID tid, MPPTAGEBranchInfo &bi, argument
435 MultiperspectivePerceptronTAGE::computePartialSum(ThreadID tid, argument
187 updateHistories( ThreadID tid, Addr branch_pc, bool taken, TAGEBase::BranchInfo* b, bool speculative, const StaticInstPtr &inst, Addr target) argument
447 updatePartial(ThreadID tid, MPPTAGEBranchInfo &bi, bool taken) argument
471 updateHistories(ThreadID tid, MPPTAGEBranchInfo &bi, bool taken) argument
527 lookup(ThreadID tid, Addr instPC, void * &bp_history) argument
559 condBranchUpdate(ThreadID tid, Addr branch_pc, bool taken, StatisticalCorrector::BranchInfo *bi, Addr corrTarget, bool bias_bit, int hitBank, int altBank, int64_t phist) argument
600 update(ThreadID tid, Addr instPC, bool taken, void *bp_history, bool squashed, const StaticInstPtr & inst, Addr corrTarget) argument
682 uncondBranch(ThreadID tid, Addr pc, void * &bp_history) argument
692 squash(ThreadID tid, void *bp_history) argument
[all...] |
| /gem5/src/cpu/ |
| H A D | base.hh | 226 getInterruptController(ThreadID tid) argument
238 postInterrupt(ThreadID tid, int int_num, int index) argument
246 clearInterrupt(ThreadID tid, int int_num, int index) argument
252 clearInterrupts(ThreadID tid) argument
445 unserializeThread(CheckpointIn &cp, ThreadID tid) argument
643 getCpuAddrMonitor(ThreadID tid) argument
[all...] |
| H A D | base_dyn_inst.hh | 916 void setTid(ThreadID tid) { threadNumber = tid; } argument
|
| /gem5/src/cpu/minor/ |
| H A D | execute.cc | 194 Execute::getInput(ThreadID tid) argument
207 popInput(ThreadID tid) argument
295 updateBranchData( ThreadID tid, BranchData::Reason reason, MinorDynInstPtr inst, const TheISA::PCState &target, BranchData &branch) argument
1601 ThreadID tid = interruptPriority; local
[all...] |
| /gem5/src/sim/ |
| H A D | syscall_emul.hh | 2328 int tid = process->getSyscallArg(tc, index); local
|