Lines Matching defs:tid
144 for (ThreadID tid = 0; tid < numThreads; tid++) {
145 decoder[tid] = new TheISA::Decoder(params->isa[tid]);
148 fetchBuffer[tid] = new uint8_t[fetchBufferSize];
334 DefaultFetch<Impl>::clearStates(ThreadID tid)
336 fetchStatus[tid] = Running;
337 pc[tid] = cpu->pcState(tid);
338 fetchOffset[tid] = 0;
339 macroop[tid] = NULL;
340 delayedCommit[tid] = false;
341 memReq[tid] = NULL;
342 stalls[tid].decode = false;
343 stalls[tid].drain = false;
344 fetchBufferPC[tid] = 0;
345 fetchBufferValid[tid] = false;
346 fetchQueue[tid].clear();
349 // priorityList.push_back(tid);
363 for (ThreadID tid = 0; tid < numThreads; ++tid) {
364 fetchStatus[tid] = Running;
365 pc[tid] = cpu->pcState(tid);
366 fetchOffset[tid] = 0;
367 macroop[tid] = NULL;
369 delayedCommit[tid] = false;
370 memReq[tid] = NULL;
372 stalls[tid].decode = false;
373 stalls[tid].drain = false;
375 fetchBufferPC[tid] = 0;
376 fetchBufferValid[tid] = false;
378 fetchQueue[tid].clear();
380 priorityList.push_back(tid);
391 ThreadID tid = cpu->contextToThread(pkt->req->contextId());
393 DPRINTF(Fetch, "[tid:%i] Waking up from cache miss.\n", tid);
398 if (fetchStatus[tid] != IcacheWaitResponse ||
399 pkt->req != memReq[tid]) {
405 memcpy(fetchBuffer[tid], pkt->getConstPtr<uint8_t>(), fetchBufferSize);
406 fetchBufferValid[tid] = true;
412 DPRINTF(Activity, "[tid:%i] Activating fetch due to cache completion\n",
413 tid);
418 if (checkStall(tid)) {
419 fetchStatus[tid] = Blocked;
421 fetchStatus[tid] = IcacheAccessComplete;
428 memReq[tid] = NULL;
501 DefaultFetch<Impl>::drainStall(ThreadID tid)
504 assert(!stalls[tid].drain);
505 DPRINTF(Drain, "%i: Thread drained.\n", tid);
506 stalls[tid].drain = true;
547 DefaultFetch<Impl>::deactivateThread(ThreadID tid)
550 auto thread_it = std::find(priorityList.begin(), priorityList.end(), tid);
573 ThreadID tid = inst->threadNumber;
575 nextPC, tid);
578 DPRINTF(Fetch, "[tid:%i] [sn:%llu] Branch at PC %#x "
580 tid, inst->seqNum, inst->pcState().instAddr(), nextPC);
582 DPRINTF(Fetch, "[tid:%i] [sn:%llu] Branch at PC %#x "
584 tid, inst->seqNum, inst->pcState().instAddr());
587 DPRINTF(Fetch, "[tid:%i] [sn:%llu] Branch at PC %#x "
589 tid, inst->seqNum, inst->pcState().instAddr(), nextPC);
604 DefaultFetch<Impl>::fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc)
613 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, cache blocked\n",
614 tid);
616 } else if (checkInterrupt(pc) && !delayedCommit[tid]) {
621 DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n",
622 tid);
629 DPRINTF(Fetch, "[tid:%i] Fetching cache line %#x for addr %#x\n",
630 tid, fetchBufferBlockPC, vaddr);
636 tid, fetchBufferBlockPC, fetchBufferSize,
638 cpu->thread[tid]->contextId());
642 memReq[tid] = mem_req;
645 fetchStatus[tid] = ItlbWait;
647 cpu->itb->translateTiming(mem_req, cpu->thread[tid]->getTC(),
657 ThreadID tid = cpu->contextToThread(mem_req->contextId());
665 if (fetchStatus[tid] != ItlbWait || mem_req != memReq[tid] ||
666 mem_req->getVaddr() != memReq[tid]->getVaddr()) {
667 DPRINTF(Fetch, "[tid:%i] Ignoring itlb completed after squash\n",
668 tid);
682 fetchStatus[tid] = NoGoodAddr;
683 memReq[tid] = NULL;
691 fetchBufferPC[tid] = fetchBufferBlockPC;
692 fetchBufferValid[tid] = false;
701 DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
703 fetchStatus[tid] = IcacheWaitRetry;
705 retryTid = tid;
708 DPRINTF(Fetch, "[tid:%i] Doing Icache access.\n", tid);
709 DPRINTF(Activity, "[tid:%i] Activity: Waiting on I-cache "
710 "response.\n", tid);
711 lastIcacheStall[tid] = curTick();
712 fetchStatus[tid] = IcacheWaitResponse;
719 if (!(numInst < fetchWidth) || !(fetchQueue[tid].size() < fetchQueueSize)) {
727 DPRINTF(Fetch, "[tid:%i] Got back req with addr %#x but expected %#x\n",
728 tid, mem_req->getVaddr(), memReq[tid]->getVaddr());
730 memReq[tid] = NULL;
735 TheISA::PCState fetchPC = pc[tid];
737 DPRINTF(Fetch, "[tid:%i] Translation faulted, building noop.\n", tid);
739 DynInstPtr instruction = buildInst(tid, StaticInst::nopStaticInstPtr,
750 fetchStatus[tid] = TrapPending;
752 DPRINTF(Fetch, "[tid:%i] Blocked, need to handle the trap.\n", tid);
753 DPRINTF(Fetch, "[tid:%i] fault (%s) detected @ PC %s.\n",
754 tid, fault->name(), pc[tid]);
762 const DynInstPtr squashInst, ThreadID tid)
764 DPRINTF(Fetch, "[tid:%i] Squashing, setting PC to: %s.\n",
765 tid, newPC);
767 pc[tid] = newPC;
768 fetchOffset[tid] = 0;
770 macroop[tid] = squashInst->macroop;
772 macroop[tid] = NULL;
773 decoder[tid]->reset();
776 if (fetchStatus[tid] == IcacheWaitResponse) {
777 DPRINTF(Fetch, "[tid:%i] Squashing outstanding Icache miss.\n",
778 tid);
779 memReq[tid] = NULL;
780 } else if (fetchStatus[tid] == ItlbWait) {
781 DPRINTF(Fetch, "[tid:%i] Squashing outstanding ITLB miss.\n",
782 tid);
783 memReq[tid] = NULL;
787 if (retryTid == tid) {
796 fetchStatus[tid] = Squashing;
799 fetchQueue[tid].clear();
806 delayedCommit[tid] = true;
815 const InstSeqNum seq_num, ThreadID tid)
817 DPRINTF(Fetch, "[tid:%i] Squashing from decode.\n", tid);
819 doSquash(newPC, squashInst, tid);
823 cpu->removeInstsUntil(seq_num, tid);
828 DefaultFetch<Impl>::checkStall(ThreadID tid) const
832 if (stalls[tid].drain) {
834 DPRINTF(Fetch,"[tid:%i] Drain stall detected.\n",tid);
850 ThreadID tid = *threads++;
852 if (fetchStatus[tid] == Running ||
853 fetchStatus[tid] == Squashing ||
854 fetchStatus[tid] == IcacheAccessComplete) {
857 DPRINTF(Activity, "[tid:%i] Activating stage.\n",tid);
859 if (fetchStatus[tid] == IcacheAccessComplete) {
860 DPRINTF(Activity, "[tid:%i] Activating fetch due to cache"
861 "completion\n",tid);
885 ThreadID tid)
887 DPRINTF(Fetch, "[tid:%i] Squash from commit.\n", tid);
889 doSquash(newPC, squashInst, tid);
892 cpu->removeInstsNotInROB(tid);
910 ThreadID tid = *threads++;
914 bool updated_status = checkSignalsAndUpdate(tid);
956 for (auto tid : *activeThreads) {
957 if (!stalls[tid].decode) {
958 available_insts += fetchQueue[tid].size();
967 ThreadID tid = *tid_itr;
968 if (!stalls[tid].decode && !fetchQueue[tid].empty()) {
969 const auto& inst = fetchQueue[tid].front();
971 DPRINTF(Fetch, "[tid:%i] [sn:%llu] Sending instruction to decode "
973 tid, inst->seqNum, fetchQueue[tid].size());
976 fetchQueue[tid].pop_front();
999 DefaultFetch<Impl>::checkSignalsAndUpdate(ThreadID tid)
1002 if (fromDecode->decodeBlock[tid]) {
1003 stalls[tid].decode = true;
1006 if (fromDecode->decodeUnblock[tid]) {
1007 assert(stalls[tid].decode);
1008 assert(!fromDecode->decodeBlock[tid]);
1009 stalls[tid].decode = false;
1013 if (fromCommit->commitInfo[tid].squash) {
1015 DPRINTF(Fetch, "[tid:%i] Squashing instructions due to squash "
1016 "from commit.\n",tid);
1018 squash(fromCommit->commitInfo[tid].pc,
1019 fromCommit->commitInfo[tid].doneSeqNum,
1020 fromCommit->commitInfo[tid].squashInst, tid);
1025 if (fromCommit->commitInfo[tid].mispredictInst &&
1026 fromCommit->commitInfo[tid].mispredictInst->isControl()) {
1027 branchPred->squash(fromCommit->commitInfo[tid].doneSeqNum,
1028 fromCommit->commitInfo[tid].pc,
1029 fromCommit->commitInfo[tid].branchTaken,
1030 tid);
1032 branchPred->squash(fromCommit->commitInfo[tid].doneSeqNum,
1033 tid);
1037 } else if (fromCommit->commitInfo[tid].doneSeqNum) {
1040 branchPred->update(fromCommit->commitInfo[tid].doneSeqNum, tid);
1044 if (fromDecode->decodeInfo[tid].squash) {
1045 DPRINTF(Fetch, "[tid:%i] Squashing instructions due to squash "
1046 "from decode.\n",tid);
1049 if (fromDecode->decodeInfo[tid].branchMispredict) {
1050 branchPred->squash(fromDecode->decodeInfo[tid].doneSeqNum,
1051 fromDecode->decodeInfo[tid].nextPC,
1052 fromDecode->decodeInfo[tid].branchTaken,
1053 tid);
1055 branchPred->squash(fromDecode->decodeInfo[tid].doneSeqNum,
1056 tid);
1059 if (fetchStatus[tid] != Squashing) {
1062 fromDecode->decodeInfo[tid].nextPC);
1064 squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
1065 fromDecode->decodeInfo[tid].squashInst,
1066 fromDecode->decodeInfo[tid].doneSeqNum,
1067 tid);
1073 if (checkStall(tid) &&
1074 fetchStatus[tid] != IcacheWaitResponse &&
1075 fetchStatus[tid] != IcacheWaitRetry &&
1076 fetchStatus[tid] != ItlbWait &&
1077 fetchStatus[tid] != QuiescePending) {
1078 DPRINTF(Fetch, "[tid:%i] Setting to blocked\n",tid);
1080 fetchStatus[tid] = Blocked;
1085 if (fetchStatus[tid] == Blocked ||
1086 fetchStatus[tid] == Squashing) {
1089 DPRINTF(Fetch, "[tid:%i] Done squashing, switching to running.\n",
1090 tid);
1092 fetchStatus[tid] = Running;
1104 DefaultFetch<Impl>::buildInst(ThreadID tid, StaticInstPtr staticInst,
1114 instruction->setTid(tid);
1116 instruction->setASID(tid);
1118 instruction->setThreadState(cpu->thread[tid]);
1120 DPRINTF(Fetch, "[tid:%i] Instruction PC %#x (%d) created "
1121 "[sn:%lli].\n", tid, thisPC.instAddr(),
1124 DPRINTF(Fetch, "[tid:%i] Instruction is: %s\n", tid,
1131 cpu->getTracer()->getInstRecord(curTick(), cpu->tcBase(tid),
1144 fetchQueue[tid].push_back(instruction);
1145 assert(fetchQueue[tid].size() <= fetchQueueSize);
1146 DPRINTF(Fetch, "[tid:%i] Fetch queue entry created (%i/%i).\n",
1147 tid, fetchQueue[tid].size(), fetchQueueSize);
1151 delayedCommit[tid] = instruction->isDelayedCommit();
1163 ThreadID tid = getFetchingThread();
1167 if (tid == InvalidThreadID) {
1178 DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid);
1181 TheISA::PCState thisPC = pc[tid];
1183 Addr pcOffset = fetchOffset[tid];
1191 if (fetchStatus[tid] == IcacheAccessComplete) {
1192 DPRINTF(Fetch, "[tid:%i] Icache miss is complete.\n", tid);
1194 fetchStatus[tid] = Running;
1196 } else if (fetchStatus[tid] == Running) {
1203 if (!(fetchBufferValid[tid] && fetchBufferBlockPC == fetchBufferPC[tid])
1204 && !inRom && !macroop[tid]) {
1205 DPRINTF(Fetch, "[tid:%i] Attempting to translate and read "
1206 "instruction, starting at PC %s.\n", tid, thisPC);
1208 fetchCacheLine(fetchAddr, tid, thisPC.instAddr());
1210 if (fetchStatus[tid] == IcacheWaitResponse)
1212 else if (fetchStatus[tid] == ItlbWait)
1217 } else if ((checkInterrupt(thisPC.instAddr()) && !delayedCommit[tid])) {
1222 DPRINTF(Fetch, "[tid:%i] Fetch is stalled!\n", tid);
1226 if (fetchStatus[tid] == Idle) {
1228 DPRINTF(Fetch, "[tid:%i] Fetch is idle!\n", tid);
1240 StaticInstPtr curMacroop = macroop[tid];
1246 DPRINTF(Fetch, "[tid:%i] Adding instructions to queue to "
1247 "decode.\n", tid);
1257 reinterpret_cast<TheISA::MachInst *>(fetchBuffer[tid]);
1260 unsigned blkOffset = (fetchAddr - fetchBufferPC[tid]) / instSize;
1265 while (numInst < fetchWidth && fetchQueue[tid].size() < fetchQueueSize
1271 !decoder[tid]->instReady();
1278 if (!fetchBufferValid[tid] ||
1279 fetchBufferBlockPC != fetchBufferPC[tid])
1289 decoder[tid]->moreBytes(thisPC, fetchAddr, inst);
1291 if (decoder[tid]->needMoreBytes()) {
1302 if (decoder[tid]->instReady()) {
1303 staticInst = decoder[tid]->decode(thisPC);
1334 buildInst(tid, staticInst, curMacroop,
1365 blkOffset = (fetchAddr - fetchBufferPC[tid]) / instSize;
1373 fetchStatus[tid] = QuiescePending;
1378 } while ((curMacroop || decoder[tid]->instReady()) &&
1380 fetchQueue[tid].size() < fetchQueueSize);
1388 DPRINTF(Fetch, "[tid:%i] Done fetching, predicted branch "
1389 "instruction encountered.\n", tid);
1391 DPRINTF(Fetch, "[tid:%i] Done fetching, reached fetch bandwidth "
1392 "for this cycle.\n", tid);
1394 DPRINTF(Fetch, "[tid:%i] Done fetching, reached the end of the"
1395 "fetch buffer.\n", tid);
1398 macroop[tid] = curMacroop;
1399 fetchOffset[tid] = pcOffset;
1405 pc[tid] = thisPC;
1411 issuePipelinedIfetch[tid] = fetchBufferBlockPC != fetchBufferPC[tid] &&
1412 fetchStatus[tid] != IcacheWaitResponse &&
1413 fetchStatus[tid] != ItlbWait &&
1414 fetchStatus[tid] != IcacheWaitRetry &&
1415 fetchStatus[tid] != QuiescePending &&
1473 ThreadID tid = *thread;
1475 if (fetchStatus[tid] == Running ||
1476 fetchStatus[tid] == IcacheAccessComplete ||
1477 fetchStatus[tid] == Idle) {
1478 return tid;
1529 ThreadID tid = *threads++;
1530 unsigned iqCount = fromIEW->iewInfo[tid].iqCount;
1532 //we can potentially get tid collisions if two threads
1535 threadMap[iqCount] = tid;
1566 ThreadID tid = *threads++;
1567 unsigned ldstqCount = fromIEW->iewInfo[tid].ldstqCount;
1569 //we can potentially get tid collisions if two threads
1572 threadMap[ldstqCount] = tid;
1599 DefaultFetch<Impl>::pipelineIcacheAccesses(ThreadID tid)
1601 if (!issuePipelinedIfetch[tid]) {
1606 TheISA::PCState thisPC = pc[tid];
1612 Addr pcOffset = fetchOffset[tid];
1619 if (!(fetchBufferValid[tid] && fetchBufferBlockPC == fetchBufferPC[tid])) {
1620 DPRINTF(Fetch, "[tid:%i] Issuing a pipelined I-cache access, "
1621 "starting at PC %s.\n", tid, thisPC);
1623 fetchCacheLine(fetchAddr, tid, thisPC.instAddr());
1629 DefaultFetch<Impl>::profileStall(ThreadID tid) {
1634 if (stalls[tid].drain) {
1640 } else if (fetchStatus[tid] == Blocked) {
1642 DPRINTF(Fetch, "[tid:%i] Fetch is blocked!\n", tid);
1643 } else if (fetchStatus[tid] == Squashing) {
1645 DPRINTF(Fetch, "[tid:%i] Fetch is squashing!\n", tid);
1646 } else if (fetchStatus[tid] == IcacheWaitResponse) {
1648 DPRINTF(Fetch, "[tid:%i] Fetch is waiting cache response!\n",
1649 tid);
1650 } else if (fetchStatus[tid] == ItlbWait) {
1652 DPRINTF(Fetch, "[tid:%i] Fetch is waiting ITLB walk to "
1653 "finish!\n", tid);
1654 } else if (fetchStatus[tid] == TrapPending) {
1656 DPRINTF(Fetch, "[tid:%i] Fetch is waiting for a pending trap!\n",
1657 tid);
1658 } else if (fetchStatus[tid] == QuiescePending) {
1660 DPRINTF(Fetch, "[tid:%i] Fetch is waiting for a pending quiesce "
1661 "instruction!\n", tid);
1662 } else if (fetchStatus[tid] == IcacheWaitRetry) {
1664 DPRINTF(Fetch, "[tid:%i] Fetch is waiting for an I-cache retry!\n",
1665 tid);
1666 } else if (fetchStatus[tid] == NoGoodAddr) {
1667 DPRINTF(Fetch, "[tid:%i] Fetch predicted non-executable address\n",
1668 tid);
1670 DPRINTF(Fetch, "[tid:%i] Unexpected fetch stall reason "
1672 tid, fetchStatus[tid]);