stats: Update stats to reflect cache changes

stats: Update stats to reflect recent changes to floats

Mostly just splitting out the floats ops and corresponding
reads/writes.

stats: Update to match classic memory changes

stats: update references

stats: update references

stats: Update stats to reflect ARM changes

stats: Add power stats to test references

Change-Id: Ic827213134b199446822f128b81d4a480e777fee

stats: Update to match ARM ISA changes

stats: update and fix e273e86a873d

stats: update for snoop filter tweak

stats: Update stats to reflect cache changes

Removed unused stats, now counting WriteLineReq, and changed how
uncacheable writes are handled while responses are outstanding.

stats: Update stats to reflect changes to cache and crossbar

stats: update stats to after GPU checkin

stats: bump stats to reflect ruby tester changes

stats: Update to reflect changes to PCI handling

stats: Update to reflect changes to RealView platform code

stats: updates due to recent chagnesets

stats: Update stats to match cache changes

stats: Update stats to reflect snoop-filter changes

stats: Update ARM stats to include programmable oscillators

stats: Update stats for cache, crossbar and DRAM changes

This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.

Needless to say, almost every regression is affected.

stats: Update stats to reflect cache changes

stats: Update stats to reflect cache and interconnect changes

This is a bulk update of stats to match the changes to cache timing,
interconnect timing, and a few minor changes to the o3 CPU.

stats: Bump stats for decoder, TLB, prefetcher and DRAM changes

Changes due to speculative execution of an unaligned PC, introduction
of TLB stats, changes and re-work of the prefetcher, and the
introduction of rank-wise refresh in the DRAM controller.

stats: Bump stats for fixes, mostly TLB and WriteInvalidate

stats: Bump regressions to match latest changes

Updates after timezone hick-up and sorting of dictionary items in the
SimObject.

tests: Update stats no match.

Bootloader I had on my sytem was an older version with a couple of
instruction differences.

tests: Update regressions for the new kernels and various preceeding fixes.

stats: Bump stats for filter, crossbar and config changes

This patch bumps the stats to reflect the addition of the snoop filter
and snoop stats, the change from bus to crossbar, and the updates to
the ARM regressions that are now using a different CPU and cache
configuration. Lastly, some minor changes are expected due to the
activation cleanup of the CPUs.

stats: Update stats for CPU and cache changes

This patch updates the stats to reflect the fixes and changes to the
CPU (mainly the o3), and the caches.

stats: Bump stats for the fixes, and mostly DRAM controller changes

arm: Bump stats after FS config script update

This patch updates the stats to reflect the change in kernel options
needed for armv8 (but used for all FS regressions).

stats: updates due to branch predictor warming

stats: update stats for ARMv8 changes

stats: update stats for cache occupancy and clock domain changes

stats: updates due to changes to ticksToCycles()

stats: Bump stats after shifting to SimpleMemory

Match stats with new regression configs.

tests: update reference outputs

Apparently only stats.txt was updated the last time, so
this changeset updates other reference output files
(config.ini, simout, simerr, ruby.stats) so that
test output diffs should not be cluttered with irrelevant
changes. There are a few stats.txt updates too, but
they are in the minority.

stats: Cumulative stats update

This patch updates the stats to reflect the: 1) addition of the
internal queue in SimpleMemory, 2) moving of the memory class outside
FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying
burst size and interface width for the DRAM instead of relying on
cache-line size, 5) performing merging in the DRAM controller write
buffer, and 6) fixing how idle cycles are counted in the atomic and
timing CPU models.

The main reason for bundling them up is to minimise the changeset
size.

stats: Update stats for monitor, cache and bus changes

This patch removes the sparse histogram total from the CommMonitor
stats. It also bumps the stats after the unit fixes in the atomic
cache access. Lastly, it updates the stats to match the new port
ordering. All numbers are the same, and the only thing that changes is
which master corresponds to what port index.

stats: Update the stats to reflect bus and memory changes

This patch updates the stats to reflect the addition of the bus stats,
and changes to the bus layers. In addition it updates the stats to
match the addition of the static pipeline latency of the memory
conotroller and the addition of a stat tracking the bytes per
activate.

stats: Update stats to reflect SimpleDRAM changes

This patch bumps the stats to reflect the slight change in how the
retry is handled, and also the pruning of some redundant stats.

stats: Update stats for regressions using SimpleDDR3

This patch updates the regression stats to reflect that they are using
the SimpleDDR3 controller by default.

regressions: update stats due to branch predictor changes
The actual statistical values are being updated for only two tests belonging
to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others
the patch updates config.ini and name changes to statistical variables.

stats: Update stats to reflect use of SimpleDRAM

This patch bumps the stats to match the use of SimpleDRAM instead of
SimpleMemory in all inorder and O3 regressions, and also all
full-system regressions. A number of performance-related stats change,
and a whole bunch of stats are added for the memory controller.

Stats: Update stats for use of two-level builder

This patch updates the name of the l2 stats.

ARM: update stats for bp and squash fixes.

stats: update stats for icache change not allowing dirty data

Stats: Update stats for RAS and LRU fixes.

all: Update stats for memory per master and total fix.

ARM: update stats for clock frequency fix.

stats: update stats for no_value -> nan
Lots of accumulated older changes too.

ARM: Update stats for IT and conditional branch changes

ARM: Update stats for CBNZ fix.

ARM: Update stats for valgrind fix and replace config.inis which are out of date.

Stats: Fix the realview regression stats after nvmem move

This patch updates the realview regressions stats to reflect that nvmem
moved in the object hierarchy and is now under system.realview.

stats: update stats for insts/ops and master id changes

SE/FS: Make both SE and FS tests available all the time.